AMDGPU: Fix asserts on invalid register ranges

[arsenm]

Summary

If the requested SGPR was not actually aligned, it was
accepted and rounded down instead of rejected.

Also fix an assert if the range is an invalid size.

[arsenm]

Fix patch

[• tstellarAMD]

LGTM.

[nhaehnle]

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

543–548

Nitpick: Maybe rename Size to Alignment?

[arsenm]

r252009

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

struct OptionalOperand {
   AMDGPUOperand::ImmTy Type;
   bool IsBit;
   int64_t Default;
   bool (*ConvertResult)(int64_t&);
 };
 
 }
 
-static unsigned getRegClass(bool IsVgpr, unsigned RegWidth) {
+static int getRegClass(bool IsVgpr, unsigned RegWidth) {
   if (IsVgpr) {
     switch (RegWidth) {
-      default: llvm_unreachable("Unknown register width");
+      default: return -1;
       case 1: return AMDGPU::VGPR_32RegClassID;
       case 2: return AMDGPU::VReg_64RegClassID;
       case 3: return AMDGPU::VReg_96RegClassID;
       case 4: return AMDGPU::VReg_128RegClassID;
       case 8: return AMDGPU::VReg_256RegClassID;
       case 16: return AMDGPU::VReg_512RegClassID;
     }
   }
 
   switch (RegWidth) {
-    default: llvm_unreachable("Unknown register width");
+    default: return -1;
     case 1: return AMDGPU::SGPR_32RegClassID;
     case 2: return AMDGPU::SGPR_64RegClassID;
     case 4: return AMDGPU::SReg_128RegClassID;
     case 8: return AMDGPU::SReg_256RegClassID;
     case 16: return AMDGPU::SReg_512RegClassID;
   }
 }
 
if (getLexer().isNot(AsmToken::RBrac))
       return true;
 
     Parser.Lex();
     RegWidth = (RegHi - RegLo) + 1;
     if (IsVgpr) {
       // VGPR registers aren't aligned.
       RegIndexInClass = RegLo;
     } else {
       // SGPR registers are aligned.  Max alignment is 4 dwords.
-      RegIndexInClass = RegLo / std::min(RegWidth, 4u);
+      unsigned Size = std::min(RegWidth, 4u);
+      if (RegLo % Size != 0)
+        return true;
+
+      RegIndexInClass = RegLo / Size;
     }
   }
 
   const MCRegisterInfo *TRI = getContext().getRegisterInfo();
-  const MCRegisterClass RC = TRI->getRegClass(getRegClass(IsVgpr, RegWidth));
+  int RCID = getRegClass(IsVgpr, RegWidth);
+  if (RCID == -1)
+    return true;
+
+  const MCRegisterClass RC = TRI->getRegClass(RCID);
   if (RegIndexInClass >= RC.getNumRegs())
     return true;
 
   RegNo = RC.getRegister(RegIndexInClass);
   return false;
 }
 
 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {

test/MC/AMDGPU/out-of-range-registers.s

 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s
 
 s_add_i32 s104, s0, s1
 // CHECK: error: invalid operand for instruction
 
 s_add_i32 s105, s0, s1
 // CHECK: error: invalid operand for instruction
 
 v_add_i32 v256, v0, v1
 // CHECK: error: invalid operand for instruction
 
 v_add_i32 v257, v0, v1
 // CHECK: error: invalid operand for instruction
+
+s_mov_b64 s[0:17], -1
+// CHECK: error: invalid operand for instruction
+
+s_mov_b64 s[103:104], -1
+// CHECK: error: invalid operand for instruction
+
+s_mov_b64 s[104:105], -1
+// CHECK: error: invalid operand for instruction