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Differential D13735

AMDGPU: Fix off by one in register parsing
ClosedPublic

Authored by arsenm on Oct 14 2015, 10:54 AM.

Details

Reviewers
• tstellarAMD
Summary

If trying to use one past the end, this would assert.

Diff Detail

Event Timeline

arsenm updated this revision to Diff 37367.Oct 14 2015, 10:54 AM
arsenm retitled this revision from to AMDGPU: Fix off by one in register parsing.
arsenm updated this object.
arsenm added a reviewer: • tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptOct 14 2015, 10:54 AM
• tstellarAMD accepted this revision.Oct 20 2015, 3:20 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Oct 20 2015, 3:20 PM
arsenm closed this revision.Nov 3 2015, 2:53 PM

r252008

Revision Contents

PathSize
lib/
Target/
AMDGPU/
AsmParser/
9 lines
test/
MC/
AMDGPU/
14 lines

Diff 37367

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Show First 20 Lines • Show All 539 Lines • ▼ Show 20 Lines if (IsVgpr) {
// VGPR registers aren't aligned. // VGPR registers aren't aligned.
RegIndexInClass = RegLo; RegIndexInClass = RegLo;
} else { } else {
// SGPR registers are aligned. Max alignment is 4 dwords. // SGPR registers are aligned. Max alignment is 4 dwords.
RegIndexInClass = RegLo / std::min(RegWidth, 4u); RegIndexInClass = RegLo / std::min(RegWidth, 4u);
} }
} }
const MCRegisterInfo *TRC = getContext().getRegisterInfo(); const MCRegisterInfo *TRI = getContext().getRegisterInfo();
unsigned RC = getRegClass(IsVgpr, RegWidth); const MCRegisterClass RC = TRI->getRegClass(getRegClass(IsVgpr, RegWidth));
if (RegIndexInClass > TRC->getRegClass(RC).getNumRegs()) if (RegIndexInClass >= RC.getNumRegs())
return true; return true;
RegNo = TRC->getRegClass(RC).getRegister(RegIndexInClass);
RegNo = RC.getRegister(RegIndexInClass);
return false; return false;
} }
unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) { unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) || if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) ||
▲ Show 20 Lines • Show All 1,197 Lines • Show Last 20 Lines

test/MC/AMDGPU/out-of-range-registers.s

  • This file was added.
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s
s_add_i32 s104, s0, s1
// CHECK: error: invalid operand for instruction
s_add_i32 s105, s0, s1
// CHECK: error: invalid operand for instruction
v_add_i32 v256, v0, v1
// CHECK: error: invalid operand for instruction
v_add_i32 v257, v0, v1
// CHECK: error: invalid operand for instruction