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Differential D13538

AMDGPU: Fix adding redundant m0 uses
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Authored by arsenm on Oct 7 2015, 3:56 PM.

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• tstellarAMD

Summary

BuildMI already adds these since they are defined correctly now.

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arsenm updated this revision to Diff 36807.Oct 7 2015, 3:56 PM

arsenm retitled this revision from to AMDGPU: Fix adding redundant m0 uses.

arsenm updated this object.

arsenm added a reviewer: • tstellarAMD.

arsenm added a subscriber: llvm-commits.

Herald added a subscriber: arsenm. · View Herald TranscriptOct 7 2015, 3:56 PM

LGTM.

This revision is now accepted and ready to land.Oct 20 2015, 3:18 PM

r250961

Revision Contents

Path

Size

lib/

Target/

AMDGPU/

SILowerControlFlow.cpp

2 lines

Diff 36807

lib/Target/AMDGPU/SILowerControlFlow.cpp

Show First 20 Lines • Show All 432 Lines • ▼ Show 20 Lines	void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) {
int Off = MI.getOperand(4).getImm();		int Off = MI.getOperand(4).getImm();
unsigned Reg;		unsigned Reg;

computeIndirectRegAndOffset(Vec, Reg, Off);		computeIndirectRegAndOffset(Vec, Reg, Off);

MachineInstr *MovRel =		MachineInstr *MovRel =
BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)		BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
.addReg(Reg)		.addReg(Reg)
.addReg(AMDGPU::M0, RegState::Implicit)
.addReg(Vec, RegState::Implicit);		.addReg(Vec, RegState::Implicit);

LoadM0(MI, MovRel, Off);		LoadM0(MI, MovRel, Off);
}		}

void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {		void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {

MachineBasicBlock &MBB = *MI.getParent();		MachineBasicBlock &MBB = *MI.getParent();
DebugLoc DL = MI.getDebugLoc();		DebugLoc DL = MI.getDebugLoc();

unsigned Dst = MI.getOperand(0).getReg();		unsigned Dst = MI.getOperand(0).getReg();
int Off = MI.getOperand(4).getImm();		int Off = MI.getOperand(4).getImm();
unsigned Val = MI.getOperand(5).getReg();		unsigned Val = MI.getOperand(5).getReg();
unsigned Reg;		unsigned Reg;

computeIndirectRegAndOffset(Dst, Reg, Off);		computeIndirectRegAndOffset(Dst, Reg, Off);

MachineInstr *MovRel =		MachineInstr *MovRel =
BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))		BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
.addReg(Reg, RegState::Define)		.addReg(Reg, RegState::Define)
.addReg(Val)		.addReg(Val)
.addReg(AMDGPU::M0, RegState::Implicit)
.addReg(Dst, RegState::Implicit);		.addReg(Dst, RegState::Implicit);

LoadM0(MI, MovRel, Off);		LoadM0(MI, MovRel, Off);
}		}

bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {		bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
TII = static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());		TII = static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
TRI =		TRI =
▲ Show 20 Lines • Show All 138 Lines • Show Last 20 Lines