[x86] replace integer 'and' ops with packed SSE FP 'and' ops when operating on FP scalars

[spatel]

Summary

As noted in the comment, we can extend this from just 'and' ops to the other logic ops if this is a good solution.

This is related to, but does not solve:
https://llvm.org/bugs/show_bug.cgi?id=22428

[ab]

Sounds reasonable

lib/Target/X86/X86ISelLowering.cpp

24453 ↗

(On Diff #35402)

TODO -> FIXME ?

[spatel]

lib/Target/X86/X86ISelLowering.cpp

24453 ↗

(On Diff #35402)

Sure - follow-up patch coming soon. :)
Thanks for the prompt review!

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
           if (Shift + MaskSize <= VT.getSizeInBits())
             return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
                                DAG.getConstant(Shift | (MaskSize << 8), DL,
                                                VT));
         }
       }
     } // BEXTR
 
+    // If both input operands are being cast from floating point types,
+    // try to convert this into a floating point logic node to avoid
+    // unnecessary moves from SSE to integer registers.
+    // FIXME: Split this into a helper function, so it can also be used with
+    //        or/xor combining.
+    if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
+        ((Subtarget->hasSSE1() && VT == MVT::i32) ||
+         (Subtarget->hasSSE2() && VT == MVT::i64))) {
+      SDValue N00 = N0.getOperand(0);
+      SDValue N10 = N1.getOperand(0);
+      EVT N00Type = N00.getValueType();
+      EVT N10Type = N10.getValueType();
+      if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
+        SDValue FLogic = DAG.getNode(X86ISD::FAND, DL, N00Type, N00, N10);
+        return DAG.getBitcast(VT, FLogic);
+      }
+    }
+
     return SDValue();
   }
 
   // Want to form ANDNP nodes:
   // 1) In the hopes of then easily combining them with OR and AND nodes
   //    to form PBLEND/PSIGN.
   // 2) To match ANDN packed intrinsics
   if (VT != MVT::v2i64 && VT != MVT::v4i64)

llvm/trunk/test/CodeGen/X86/fp-logic.ll

; CHECK-NEXT:    retq
   ret float %bc2
 }
 
 ; 2 FP operands, int result
 
 define i32 @f9(float %x, float %y) {
 ; CHECK-LABEL: f9:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movd %xmm0, %ecx
-; CHECK-NEXT:    movd %xmm1, %eax
-; CHECK-NEXT:    andl %ecx, %eax
+; CHECK-NEXT:    andps %xmm1, %xmm0
+; CHECK-NEXT:    movd %xmm0, %eax
 ; CHECK-NEXT:    retq
 
   %bc1 = bitcast float %x to i32
   %bc2 = bitcast float %y to i32
   %and = and i32 %bc1, %bc2
   ret i32 %and
 }
 
 ; 2 FP operands, FP result
 
 define float @f10(float %x, float %y) {
 ; CHECK-LABEL: f10:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movd %xmm0, %eax
-; CHECK-NEXT:    movd %xmm1, %ecx
-; CHECK-NEXT:    andl %eax, %ecx
-; CHECK-NEXT:    movd %ecx, %xmm0
+; CHECK-NEXT:    andps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
 
   %bc1 = bitcast float %x to i32
   %bc2 = bitcast float %y to i32
   %and = and i32 %bc1, %bc2
   %bc3 = bitcast i32 %and to float
   ret float %bc3
 }
; CHECK-NEXT:    retq
   ret float %bc3
 }
 
 ; Make sure that doubles work too.
 
 define double @doubles(double %x, double %y) {
 ; CHECK-LABEL: doubles:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movd %xmm0, %rax
-; CHECK-NEXT:    movd %xmm1, %rcx
-; CHECK-NEXT:    andq %rax, %rcx
-; CHECK-NEXT:    movd %rcx, %xmm0
+; CHECK-NEXT:    andpd %xmm1, %xmm0
 ; CHECK-NEXT:    retq
 
   %bc1 = bitcast double %x to i64
   %bc2 = bitcast double %y to i64
   %and = and i64 %bc1, %bc2
   %bc3 = bitcast i64 %and to double
   ret double %bc3
 }