AMDGPU: Fix recomputing dominator tree unnecessarily

[arsenm]

Summary

SIFixSGPRCopies does not modify the CFG, but this was
being recomputed before running SIFoldOperands.

[arsenm]

Mark more passes as preserving the CFG. This saves another MachineDominatorTree run

[• tstellarAMD]

LGTM.

[arsenm]

r248587

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

public:
   SIFixSGPRCopies(TargetMachine &tm) : MachineFunctionPass(ID) { }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
     return "SI Fix SGPR copies";
   }
 
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
 };
 
 } // End anonymous namespace
 
 char SIFixSGPRCopies::ID = 0;
 
 FunctionPass *llvm::createSIFixSGPRCopiesPass(TargetMachine &tm) {
   return new SIFixSGPRCopies(tm);

lib/Target/AMDGPU/SIFoldOperands.cpp

public:
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
     return "SI Fold Operands";
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<MachineDominatorTree>();
+    AU.addPreserved<MachineDominatorTree>();
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 };
 
 struct FoldCandidate {
   MachineInstr *UseMI;
   unsigned UseOpNo;

lib/Target/AMDGPU/SIInsertWaits.cpp

SIInsertWaits(TargetMachine &tm) :
     MachineFunctionPass(ID),
     TII(nullptr),
     TRI(nullptr),
     ExpInstrTypesSeen(0) { }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
-    return "SI insert wait  instructions";
+    return "SI insert wait instructions";
   }
 
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
 };
 
 } // End anonymous namespace
 
 char SIInsertWaits::ID = 0;
 
 const Counters SIInsertWaits::WaitCounts = { { 15, 7, 7 } };
 const Counters SIInsertWaits::ZeroCounts = { { 0, 0, 0 } };

lib/Target/AMDGPU/SILowerControlFlow.cpp

SILowerControlFlowPass(TargetMachine &tm) :
     MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
     return "SI Lower control flow instructions";
   }
 
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
 };
 
 } // End anonymous namespace
 
 char SILowerControlFlowPass::ID = 0;
 
 FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
   return new SILowerControlFlowPass(tm);

lib/Target/AMDGPU/SILowerI1Copies.cpp

public:
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
     return "SI Lower i1 Copies";
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.addRequired<MachineDominatorTree>();
+    AU.addPreserved<MachineDominatorTree>();
     AU.setPreservesCFG();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 };
 
 } // End anonymous namespace.
 
 INITIALIZE_PASS_BEGIN(SILowerI1Copies, DEBUG_TYPE,

lib/Target/AMDGPU/SIPrepareScratchRegs.cpp

public:
   SIPrepareScratchRegs() : MachineFunctionPass(ID) { }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
     return "SI prepare scratch registers";
   }
 
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesCFG();
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
 };
 
 } // End anonymous namespace
 
 char SIPrepareScratchRegs::ID = 0;
 
 FunctionPass *llvm::createSIPrepareScratchRegs() {
   return new SIPrepareScratchRegs();