[X86-64] Allow additional register names in inline assembler.

[ABataev]

Summary

Patch allows to recognize additional registers x8d, x8b, x8w - x15d, x15b, x15w in inline assembler, already recognized by backend

[echristo]

If you could interleave the test and the check I'd really appreciate it, e.g.:

__asm__ ("mov r8w, 100;");

// CHECK: call void asm sideeffect "mov r8w, 100;"

Otherwise LGTM. Thanks!

-eric

[ABataev]

Eric, thanks for the review! Will do!

cfe/trunk/lib/Basic/Targets.cpp

const TargetInfo::AddlRegName AddlRegNames[] = {
   { { "al", "ah", "eax", "rax" }, 0 },
   { { "bl", "bh", "ebx", "rbx" }, 3 },
   { { "cl", "ch", "ecx", "rcx" }, 2 },
   { { "dl", "dh", "edx", "rdx" }, 1 },
   { { "esi", "rsi" }, 4 },
   { { "edi", "rdi" }, 5 },
   { { "esp", "rsp" }, 7 },
   { { "ebp", "rbp" }, 6 },
+  { { "r8d", "r8w", "r8b" }, 38 },
+  { { "r9d", "r9w", "r9b" }, 39 },
+  { { "r10d", "r10w", "r10b" }, 40 },
+  { { "r11d", "r11w", "r11b" }, 41 },
+  { { "r12d", "r12w", "r12b" }, 42 },
+  { { "r13d", "r13w", "r13b" }, 43 },
+  { { "r14d", "r14w", "r14b" }, 44 },
+  { { "r15d", "r15w", "r15b" }, 45 },
 };
 
 // X86 target abstract base class; x86-32 and x86-64 are very close, so
 // most of the implementation can be shared.
 class X86TargetInfo : public TargetInfo {
   enum X86SSEEnum {
     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
   } SSELevel;

cfe/trunk/test/CodeGen/asm_64.c

+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @t1
+void t1() {
+  __asm__ ("mov r8w, 100;");
+  // CHECK: call void asm sideeffect "mov r8w, 100;"
+  __asm__ ("mov r8d, 100;");
+  // CHECK: call void asm sideeffect "mov r8d, 100;"
+  __asm__ ("mov r8b, 100;");
+  // CHECK: call void asm sideeffect "mov r8b, 100;"
+  __asm__ ("mov r9w, 100;");
+  // CHECK: call void asm sideeffect "mov r9w, 100;"
+  __asm__ ("mov r9d, 100;");
+  // CHECK: call void asm sideeffect "mov r9d, 100;"
+  __asm__ ("mov r9b, 100;");
+  // CHECK: call void asm sideeffect "mov r9b, 100;"
+  __asm__ ("mov r10w, 100;");
+  // CHECK: call void asm sideeffect "mov r10w, 100;"
+  __asm__ ("mov r10d, 100;");
+  // CHECK: call void asm sideeffect "mov r10d, 100;"
+  __asm__ ("mov r10b, 100;");
+  // CHECK: call void asm sideeffect "mov r10b, 100;"
+  __asm__ ("mov r11w, 100;");
+  // CHECK: call void asm sideeffect "mov r11w, 100;"
+  __asm__ ("mov r11d, 100;");
+  // CHECK: call void asm sideeffect "mov r11d, 100;"
+  __asm__ ("mov r11b, 100;");
+  // CHECK: call void asm sideeffect "mov r11b, 100;"
+  __asm__ ("mov r12w, 100;");
+  // CHECK: call void asm sideeffect "mov r12w, 100;"
+  __asm__ ("mov r12d, 100;");
+  // CHECK: call void asm sideeffect "mov r12d, 100;"
+  __asm__ ("mov r12b, 100;");
+  // CHECK: call void asm sideeffect "mov r12b, 100;"
+  __asm__ ("mov r13w, 100;");
+  // CHECK: call void asm sideeffect "mov r13w, 100;"
+  __asm__ ("mov r13d, 100;");
+  // CHECK: call void asm sideeffect "mov r13d, 100;"
+  __asm__ ("mov r13b, 100;");
+  // CHECK: call void asm sideeffect "mov r13b, 100;"
+  __asm__ ("mov r14w, 100;");
+  // CHECK: call void asm sideeffect "mov r14w, 100;"
+  __asm__ ("mov r14d, 100;");
+  // CHECK: call void asm sideeffect "mov r14d, 100;"
+  __asm__ ("mov r14b, 100;");
+  // CHECK: call void asm sideeffect "mov r14b, 100;"
+  __asm__ ("mov r15w, 100;");
+  // CHECK: call void asm sideeffect "mov r15w, 100;"
+  __asm__ ("mov r15d, 100;");
+  // CHECK: call void asm sideeffect "mov r15d, 100;"
+  __asm__ ("mov r15b, 100;");
+  // CHECK: call void asm sideeffect "mov r15b, 100;"
+}