AMDGPU/SI: Fold AMDGPUISD::CLAMP into VOP3 instructions when possible

[arsenm]

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

596–597

This can be folded into the if (SDNode ...

878

I think I read somewhere that using clamp / omod doesn't work with denormals, so maybe this should be not doing this fold if hasFP32Denormals.

Does this work with f64 also?

[arsenm]

Obsoleted by D30134

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

private:
   bool SelectVOP3Mods0Clamp(SDValue In, SDValue &Src, SDValue &SrcMods,
                             SDValue &Omod) const;
   bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods,
                                  SDValue &Clamp,
                                  SDValue &Omod) const;
 
   SDNode *SelectADD_SUB_I64(SDNode *N);
   SDNode *SelectDIV_SCALE(SDNode *N);
+  SDNode *SelectCLAMP(SDNode *N);
 
   SDNode *getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
                    uint32_t Offset, uint32_t Width);
   SDNode *SelectS_BFEFromShifts(SDNode *N);
   SDNode *SelectS_BFE(SDNode *N);
 
   // Include the pieces autogenerated from the target description.
 #include "AMDGPUGenDAGISel.inc"
case AMDGPUISD::BFE_U32: {
 
     return getS_BFE(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32, SDLoc(N),
                     N->getOperand(0), OffsetVal, WidthVal);
 
   }
   case AMDGPUISD::DIV_SCALE: {
     return SelectDIV_SCALE(N);
   }
+
+  case AMDGPUISD::CLAMP: {
+    SDNode *Clamp = SelectCLAMP(N);
+    if (Clamp)
+      return Clamp;
+    break;
+  }
+
   case ISD::CopyToReg: {
     const SITargetLowering& Lowering =
       *static_cast<const SITargetLowering*>(getTargetLowering());
     Lowering.legalizeTargetIndependentNode(N, *CurDAG);
     break;
   }
   case ISD::ADDRSPACECAST:
     return SelectAddrSpaceCast(N);
SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
   SDValue Ops[8];
 
   SelectVOP3Mods0(N->getOperand(0), Ops[1], Ops[0], Ops[6], Ops[7]);
   SelectVOP3Mods(N->getOperand(1), Ops[3], Ops[2]);
   SelectVOP3Mods(N->getOperand(2), Ops[5], Ops[4]);
   return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
 }
 
+SDNode *AMDGPUDAGToDAGISel::SelectCLAMP(SDNode *N) {
+
+  SDValue N0 = N->getOperand(0);
+
+  // If the input is FABS or FNEG then we want to fallback to tablegen
+  // to make sure the clamp and the FABS or FNEG modifiers are applied
+  // to the same instructions.
+  if (!N0->hasOneUse() || N0->getOpcode() == ISD::FABS ||
+      N0->getOpcode() == ISD::FNEG)
+    return nullptr;
+
+  SDNode *SelectedN0 = SelectCode(N0.getNode());
+  if (!SelectedN0)
+    return nullptr;
+
+  int ClampIdx = AMDGPU::getNamedOperandIdx(SelectedN0->getMachineOpcode(),
+                                            AMDGPU::OpName::clamp);
+  if (ClampIdx == -1)
+    return nullptr;
+
+  // SDNodes don't have a dst operand, so we need to subtract one from the
+  // operand index.
+  ClampIdx--;
+
+  SmallVector<SDValue, 8> Ops;
+  for (int i = 0, e = SelectedN0->getNumOperands(); i != e; ++i) {
+    if (i == ClampIdx) {
+      Ops.push_back(CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32));
+      continue;
+    }
+    Ops.push_back(SelectedN0->getOperand(i));
+  }
+  CurDAG->UpdateNodeOperands(SelectedN0, Ops);
+
+  return SelectedN0;
+}
+
 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
                                          unsigned OffsetBits) const {
   if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
       (OffsetBits == 8 && !isUInt<8>(Offset)))
     return false;
 
   if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS ||
       Subtarget->unsafeDSOffsetFoldingEnabled())

test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll

 ; SI: s_load_dword [[ARG:s[0-9]+]],
 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
 ; SI: buffer_store_dword [[RESULT]]
 define void @clamp_0_1_amdil_legacy_f32(float addrspace(1)* %out, float %src) nounwind {
   %clamp = call float @llvm.AMDIL.clamp.f32(float %src, float 0.0, float 1.0) nounwind readnone
   store float %clamp, float addrspace(1)* %out, align 4
   ret void
 }
+
+; FUNC-LABEL: {{^}}clamp_fold:
+; SI: v_mul_f32_e64 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}} clamp
+define void @clamp_fold(float addrspace(1)* %out, float %src) {
+  %tmp0 = fmul float %src, 10.0
+  %clamp = call float @llvm.AMDGPU.clamp.f32(float %tmp0, float 0.0, float 1.0) readnone
+  store float %clamp, float addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}clamp_no_fold:
+; SI: v_mul_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+$}}
+define void @clamp_no_fold(float addrspace(1)* %out, float %src) {
+  %tmp0 = fmul float %src, 10.0
+  %clamp = call float @llvm.AMDGPU.clamp.f32(float %tmp0, float 0.0, float 1.0) readnone
+  %tmp1 = fmul float %tmp0, %clamp
+  store float %tmp1, float addrspace(1)* %out, align 4
+  ret void
+}
+
 ; FUNC-LABEL: {{^}}clamp_non_standard:
 ; SI-DAG: v_max_f32
 ; SI-DAG: v_min_f32
 define void @clamp_non_standard(float addrspace(1)* %out, float %src) {
   %clamp = call float @llvm.AMDGPU.clamp.f32(float %src, float -1.0, float 1.0) readnone
   store float %clamp, float addrspace(1)* %out, align 4
   ret void
 }