Emit <regmask R1 R2 R3 ...> instead of just <regmask> in IR dumps.

[qcolombet]

Hi Daniel,

Sometimes masks are quite big. I wonder if this behavior should be behind a flag, maybe on by default though.

Cheers,
-Quentin

lib/CodeGen/MachineInstr.cpp

420

I would have expected the loop to look a bit differently to avoid the divide and modulo:
const uint32_t *MaskWord = getRegMask();
unsigned BaseIdx = 0;
for (; MaskWord; ++MaskWord, BaseIdx += 32) {

for (unsigned Idx = BaseIdx; Offset < BaseIdx + 32; ++Offset)
  OS << " " << PrintReg(Idx, TRI);

}

[dsanders]

Sometimes masks are quite big. I wonder if this behavior should be behind a flag, maybe on by default though.

Ok. I'll post an updated patch that adds an option shortly.

lib/CodeGen/MachineInstr.cpp

420

A good compiler will reduce the divide and modulo to 'x>>5' and 'x&31', but I thought it was clearer to use 'x/32' and 'x%32' in the source.

const uint32_t *MaskWord = getRegMask();
unsigned BaseIdx = 0;
for (; MaskWord; ++MaskWord, BaseIdx += 32) {

for (unsigned Idx = BaseIdx; Offset < BaseIdx + 32; ++Offset)
  OS << " " << PrintReg(Idx, TRI);

}

I don't think this loop works correctly. The array can have runs of zero words inside it and is not guaranteed to end in a zero word.

[kparzysz]

Or it can print up to a certain number of registers (by default) followed by ..., e.g <regmask R1 R2 R3 R4 R5 ...>. Then an option could be used to print all of them.

Edit: I just noticed that the title of the page shows the regmask in exactly that form (the actual code does not, though).

[qcolombet]

lib/CodeGen/MachineInstr.cpp

420

I don't think this loop works correctly. The array can have runs of zero words inside it and is not guaranteed to end in a zero word.

Of course, you’re right. I must have mixed that with another API :).

[dsanders]

Add an option to print the whole regmask (currently on by default but I don't
mind either way). When disabled, the first 10 will be printed followed by
"and %d more...".

[qcolombet]

Hi Daniel,

LGTM.

Thanks,
-Quentin

lib/CodeGen/MachineInstr.cpp

 #include "llvm/IR/LLVMContext.h"
 #include "llvm/IR/Metadata.h"
 #include "llvm/IR/Module.h"
 #include "llvm/IR/ModuleSlotTracker.h"
 #include "llvm/IR/Type.h"
 #include "llvm/IR/Value.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCSymbol.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 using namespace llvm;
 
+static cl::opt<bool> PrintWholeRegMask(
+    "print-whole-regmask",
+    cl::desc("Print the full contents of regmask operands in IR dumps"),
+    cl::init(true), cl::Hidden);
+
 //===----------------------------------------------------------------------===//
 // MachineOperand Implementation
 //===----------------------------------------------------------------------===//
 
 void MachineOperand::setReg(unsigned Reg) {
   if (getReg() == Reg) return; // No change.
 
   // Otherwise, we have to change the register.  If this operand is embedded
case MachineOperand::MO_ExternalSymbol:
     OS << '>';
     break;
   case MachineOperand::MO_BlockAddress:
     OS << '<';
     getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
     if (getOffset()) OS << "+" << getOffset();
     OS << '>';
     break;
-  case MachineOperand::MO_RegisterMask:
-    OS << "<regmask>";
+  case MachineOperand::MO_RegisterMask: {
+    unsigned NumRegsInMask = 0;
+    unsigned NumRegsEmitted = 0;
+    OS << "<regmask";
+    for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
+      unsigned MaskWord = i / 32;
+      unsigned MaskBit = i % 32;
+      if (getRegMask()[MaskWord] & (1 << MaskBit)) {
+        if (PrintWholeRegMask || NumRegsEmitted <= 10) {
+          OS << " " << PrintReg(i, TRI);
+          NumRegsEmitted++;
+        }
+        NumRegsInMask++;
+      }
+    }
+    if (NumRegsEmitted != NumRegsInMask)
+      OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
+    OS << ">";
     break;
+  }
   case MachineOperand::MO_RegisterLiveOut:
     OS << "<regliveout>";
     break;
   case MachineOperand::MO_Metadata:
     OS << '<';
     getMetadata()->printAsOperand(OS, MST);
     OS << '>';
     break;