AMDGPU: Set SubRegIndex size and offset

[arsenm]

Summary

I'm not sure what reasons the comment here could have had for not setting these. Without these set, there is an assertion hit during DWARF emission.

[• tstellarAMD]

This patch LGTM.

[arsenm]

r243661

lib/Target/AMDGPU/AMDGPURegisterInfo.td

 //===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // Tablegen register definitions common to all hw codegen targets.
 //
 //===----------------------------------------------------------------------===//
 
 let Namespace = "AMDGPU" in {
 
 foreach Index = 0-15 in {
-  // Indices are used in a variety of ways here, so don't set a size/offset.
-  def sub#Index : SubRegIndex<-1, -1>;
+  def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
 }
 
 def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;
 
 }
 
 include "R600RegisterInfo.td"
 include "SIRegisterInfo.td"