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Differential D11610

[mips][FastISel] Remove hidden mips-fast-isel option.
ClosedPublic

Authored by vkalintiris on Jul 29 2015, 2:36 PM.

Details

Reviewers
dsanders
Commits
rGdb9a51ac9f00: Merging r243638 and r243640: --------------------------------------------------…
rG2041b1dd0bf7: [mips][FastISel] Remove hidden mips-fast-isel option.
rL243638: [mips][FastISel] Remove hidden mips-fast-isel option.
Summary

This hidden option would disable code generation through FastISel by
default. It was removed from the available options and from the
Fast-ISel tests that required it in order to run the tests.

Diff Detail

Repository
rL LLVM

Event Timeline

vkalintiris updated this revision to Diff 30948.Jul 29 2015, 2:36 PM
vkalintiris retitled this revision from to [mips][FastISel] Remove hidden mips-fast-isel option..
vkalintiris updated this object.
vkalintiris added a reviewer: dsanders.
vkalintiris added a subscriber: llvm-commits.
Herald added a subscriber: qcolombet. · View Herald TranscriptJul 29 2015, 2:36 PM
echristo added a subscriber: echristo.Jul 29 2015, 3:15 PM

Hi, some inline comments :)

-eric

test/CodeGen/Mips/Fast-ISel/bswap1.ll
2–5 ↗(On Diff #30948)

You shouldn't need -fast-isel=true on these lines any more.

test/CodeGen/Mips/Fast-ISel/div1.ll
2–4 ↗(On Diff #30948)

Ditto.

test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll
2 ↗(On Diff #30948)

Ditto.

test/CodeGen/Mips/Fast-ISel/logopm.ll
1–2 ↗(On Diff #30948)

Ditto.

test/CodeGen/Mips/Fast-ISel/memtest1.ll
2–5 ↗(On Diff #30948)

Again.

test/CodeGen/Mips/Fast-ISel/mul1.ll
2–4 ↗(On Diff #30948)

Ditto.

test/CodeGen/Mips/Fast-ISel/rem1.ll
2–4 ↗(On Diff #30948)

Ditto.

test/CodeGen/Mips/Fast-ISel/sel1.ll
2 ↗(On Diff #30948)

Ditto.

test/CodeGen/Mips/Fast-ISel/shift.ll
1 ↗(On Diff #30948)

Why -O1 here?

test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
2 ↗(On Diff #30948)

The typical thing is to just use llc -march here, but I gather optimization makes the testcase go away?

7 ↗(On Diff #30948)

Go ahead and clean this up separately.

vkalintiris updated this revision to Diff 30968.Jul 29 2015, 4:52 PM
vkalintiris marked 8 inline comments as done.

Removed needless instances of the -fast-isel option from the FastISel tests.

vkalintiris added a comment.Jul 29 2015, 4:53 PM

Hi Eric,

Thanks for your comments. I replaced -mips-fast-isel with sed and forgot to do the same for -fast-isel. It should be fine now.

Thanks,
Vasileios

test/CodeGen/Mips/Fast-ISel/sel1.ll
2 ↗(On Diff #30948)

I believe that this one is required because of the -O2 level. Otherwise, I get the following assert error:

Assertion `(!EnableFastISelAbort || TM.Options.EnableFastISel) && "-fast-isel-abort > 0 requires -fast-isel"

Would you like me to change the level and whatever CHECK-lines are needed in this review? There are several things that we have to clean-up in FastISel and it's my intention to do that after the upcoming release.

test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
2 ↗(On Diff #30948)

That's right. However, we need the function's attributes too. This fine balance of options forces the OptLevelChanger to change the function's opt-level from -O2 to -O0. With -debug-only=isel, I get the following output:

...
Changing optimization level for Function main
        Before: -O2 ; After: -O0             
....

I had to try by trial and error in order to get it right, after reading about this behaviour from lib/CodeGen/SelectionDag/SelectionDagISel.cpp and the comments at test/CodeGen/X86/dag-optnone.ll

dsanders accepted this revision.Jul 30 2015, 4:07 AM
dsanders edited edge metadata.

It will LGTM with the attribute issue resolved. It seems excessive for this small detail to block merging to the release branch though so I don't mind if you commit and resolve that bit in a follow up.

test/CodeGen/Mips/Fast-ISel/sel1.ll
2 ↗(On Diff #30968)

I agree that this one is necessary since Fast ISel isn't the default for -O2

test/CodeGen/Mips/emergency-spill-slot-near-fp.ll
2 ↗(On Diff #30968)

However, we need the function's attributes too.

I don't entirely follow why we need the attributes. FastISel off-by-default and on-by-default but explicitly disabled should have the same effect.
Also, the 'Changing optimization level' message you mentioned looks like it's just applying the effect of the -O0 command line option.

There's some dubious looking code in OptLevelChanger's constructor that enables FastISel without consulting the command-line option like LLVMTargetMachine.cpp's addPassesToGenerateCode does. Are we sure that -fast-isel=false works?

This revision is now accepted and ready to land.Jul 30 2015, 4:07 AM
vkalintiris added a subscriber: vkalintiris.Jul 30 2015, 5:39 AM

Hi Daniel,

I tried to take a quick look into the issue but I can't figure out exactly what's going on. I will commit this so that we can merge it to the release branch. I completely agree with you that in principle -fast-isel=false shouldn't produce any different output with/without this patch. However, I'll look it more thoroughly over the weekend by tracing the execution of llc with and without FastISel enabled.

Thanks,
V. Kalintiris

Closed by commit rL243638: [mips][FastISel] Remove hidden mips-fast-isel option. (authored by vkalintiris). · Explain WhyJul 30 2015, 5:40 AM
This revision was automatically updated to reflect the committed changes.
dsanders added a comment.Jul 30 2015, 6:07 AM

Ok, Thanks.

Revision Contents

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Mips/
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CodeGen/
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Fast-ISel/
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Diff 31020

llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

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#include "llvm/ADT/Statistic.h" #include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallingConv.h" #include "llvm/IR/CallingConv.h"
#include "llvm/IR/DerivedTypes.h" #include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/GlobalVariable.h" #include "llvm/IR/GlobalVariable.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
Show All 10 Lines
LargeGOT("mxgot", cl::Hidden, LargeGOT("mxgot", cl::Hidden,
cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
static cl::opt<bool> static cl::opt<bool>
NoZeroDivCheck("mno-check-zero-division", cl::Hidden, NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
cl::desc("MIPS: Don't trap on integer division by zero."), cl::desc("MIPS: Don't trap on integer division by zero."),
cl::init(false)); cl::init(false));
cl::opt<bool>
EnableMipsFastISel("mips-fast-isel", cl::Hidden,
cl::desc("Allow mips-fast-isel to be used"),
cl::init(false));
static const MCPhysReg Mips64DPRegs[8] = { static const MCPhysReg Mips64DPRegs[8] = {
Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
}; };
// If I is a shifted mask, set the size (Size) and the first bit of the // If I is a shifted mask, set the size (Size) and the first bit of the
// mask (Pos), and return true. // mask (Pos), and return true.
// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
▲ Show 20 Lines • Show All 387 Lines • ▼ Show 20 Linesconst MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
return llvm::createMipsSETargetLowering(TM, STI); return llvm::createMipsSETargetLowering(TM, STI);
} }
// Create a fast isel object. // Create a fast isel object.
FastISel * FastISel *
MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo) const { const TargetLibraryInfo *libInfo) const {
if (!EnableMipsFastISel) if (!funcInfo.MF->getTarget().Options.EnableFastISel)
return TargetLowering::createFastISel(funcInfo, libInfo); return TargetLowering::createFastISel(funcInfo, libInfo);
return Mips::createFastISel(funcInfo, libInfo); return Mips::createFastISel(funcInfo, libInfo);
} }
EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
EVT VT) const { EVT VT) const {
if (!VT.isVector()) if (!VT.isVector())
return MVT::i32; return MVT::i32;
▲ Show 20 Lines • Show All 3,480 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/Mips/Fast-ISel/br1.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@b = global i32 1, align 4 @b = global i32 1, align 4
@i = global i32 0, align 4 @i = global i32 0, align 4
@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @br() #0 { define void @br() #0 {
Show All 23 Lines

llvm/trunk/test/CodeGen/Mips/Fast-ISel/bswap1.ll

; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s \ ; RUN: -fast-isel-abort=1 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=32R1 ; RUN: -check-prefix=ALL -check-prefix=32R1
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s \ ; RUN: -fast-isel-abort=1 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=32R2 ; RUN: -check-prefix=ALL -check-prefix=32R2
@a = global i16 -21829, align 2 @a = global i16 -21829, align 2
@b = global i32 -1430532899, align 4 @b = global i32 -1430532899, align 4
@a1 = common global i16 0, align 2 @a1 = common global i16 0, align 2
@b1 = common global i32 0, align 4 @b1 = common global i32 0, align 4
declare i16 @llvm.bswap.i16(i16) declare i16 @llvm.bswap.i16(i16)
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll

; RUN: llc -march=mipsel -mcpu=mips32 -O0 \ ; RUN: llc -march=mipsel -mcpu=mips32 -O0 \
; RUN: -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \ ; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1
; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 \ ; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 \
; RUN: -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \ ; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2
declare void @xb(i8) declare void @xb(i8)
define void @cxb() { define void @cxb() {
; ALL-LABEL: cxb: ; ALL-LABEL: cxb:
; ALL: addiu $[[T0:[0-9]+]], $zero, 10 ; ALL: addiu $[[T0:[0-9]+]], $zero, 10
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll

; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic \ ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic \
; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 < %s | FileCheck %s ; RUN: -fast-isel=true -fast-isel-abort=1 < %s | FileCheck %s
; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic \ ; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic \
; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 < %s | FileCheck %s ; RUN: -fast-isel=true -fast-isel-abort=1 < %s | FileCheck %s
@ARR = external global [10 x i32], align 4 @ARR = external global [10 x i32], align 4
define void @foo() { define void @foo() {
; CHECK-LABEL: foo ; CHECK-LABEL: foo
; CHECK-DAG: lw $[[ARR:[0-9]+]], %got(ARR)({{.*}}) ; CHECK-DAG: lw $[[ARR:[0-9]+]], %got(ARR)({{.*}})
; CHECK-DAG: addiu $[[T0:[0-9]+]], $zero, 12345 ; CHECK-DAG: addiu $[[T0:[0-9]+]], $zero, 12345
; CHECK: sw $[[T0]], 8($[[ARR]]) ; CHECK: sw $[[T0]], 8($[[ARR]])
entry: entry:
store i32 12345, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ARR, i32 0, i32 2), align 4 store i32 12345, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ARR, i32 0, i32 2), align 4
ret void ret void
} }

llvm/trunk/test/CodeGen/Mips/Fast-ISel/div1.ll

; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s ; RUN: -fast-isel-abort=1 | FileCheck %s
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s ; RUN: -fast-isel-abort=1 | FileCheck %s
@sj = global i32 200000, align 4 @sj = global i32 200000, align 4
@sk = global i32 -47, align 4 @sk = global i32 -47, align 4
@uj = global i32 200000, align 4 @uj = global i32 200000, align 4
@uk = global i32 43, align 4 @uk = global i32 43, align 4
@si = common global i32 0, align 4 @si = common global i32 0, align 4
@ui = common global i32 0, align 4 @ui = common global i32 0, align 4
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/fastalloca.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
%struct.x = type { i32 } %struct.x = type { i32 }
@i = common global i32 0, align 4 @i = common global i32 0, align 4
define i32 @foobar(i32 signext %x) { define i32 @foobar(i32 signext %x) {
entry: entry:
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/fastcc-miss.ll

; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
; RUN: -fast-isel=true -mips-fast-isel -fast-isel-verbose 2>&1 | \ ; RUN: -fast-isel-verbose 2>&1 | FileCheck %s
; RUN: FileCheck %s
; CHECK: FastISel missed call: ; CHECK: FastISel missed call:
; CHECK-SAME: %call = call fastcc i32 @foo(i32 signext %a, i32 signext %b) ; CHECK-SAME: %call = call fastcc i32 @foo(i32 signext %a, i32 signext %b)
define internal i32 @bar(i32 signext %a, i32 signext %b) { define internal i32 @bar(i32 signext %a, i32 signext %b) {
%s = and i32 %a, %b %s = and i32 %a, %b
ret i32 %s ret i32 %s
} }
define i32 @foo(i32 signext %a, i32 signext %b) { define i32 @foo(i32 signext %a, i32 signext %b) {
%call = call fastcc i32 @foo(i32 signext %a, i32 signext %b) %call = call fastcc i32 @foo(i32 signext %a, i32 signext %b)
ret i32 %call ret i32 %call
} }

llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@f1 = common global float 0.000000e+00, align 4 @f1 = common global float 0.000000e+00, align 4
@f2 = common global float 0.000000e+00, align 4 @f2 = common global float 0.000000e+00, align 4
@b1 = common global i32 0, align 4 @b1 = common global i32 0, align 4
@d1 = common global double 0.000000e+00, align 8 @d1 = common global double 0.000000e+00, align 8
@d2 = common global double 0.000000e+00, align 8 @d2 = common global double 0.000000e+00, align 8
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpext.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@f = global float 0x40147E6B80000000, align 4 @f = global float 0x40147E6B80000000, align 4
@d_f = common global double 0.000000e+00, align 8 @d_f = common global double 0.000000e+00, align 8
@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1 @.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @dv() #0 { define void @dv() #0 {
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpintconv.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@f = global float 0x40D6E83280000000, align 4 @f = global float 0x40D6E83280000000, align 4
@d = global double 0x4132D68780000000, align 8 @d = global double 0x4132D68780000000, align 8
@i_f = common global i32 0, align 4 @i_f = common global i32 0, align 4
@i_d = common global i32 0, align 4 @i_d = common global i32 0, align 4
@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/fptrunc.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@d = global double 0x40147E6B74DF0446, align 8 @d = global double 0x40147E6B74DF0446, align 8
@f = common global float 0.000000e+00, align 4 @f = common global float 0.000000e+00, align 4
@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1 @.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @fv() #0 { define void @fv() #0 {
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpa.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@c = global i32 4, align 4 @c = global i32 4, align 4
@d = global i32 9, align 4 @d = global i32 9, align 4
@uc = global i32 4, align 4 @uc = global i32 4, align 4
@ud = global i32 9, align 4 @ud = global i32 9, align 4
@b1 = common global i32 0, align 4 @b1 = common global i32 0, align 4
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/loadstore2.ll

; ModuleID = 'loadstore2.c' ; ModuleID = 'loadstore2.c'
target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64" target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
target triple = "mips--linux-gnu" target triple = "mips--linux-gnu"
@c2 = common global i8 0, align 1 @c2 = common global i8 0, align 1
@c1 = common global i8 0, align 1 @c1 = common global i8 0, align 1
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@s2 = common global i16 0, align 2 @s2 = common global i16 0, align 2
@s1 = common global i16 0, align 2 @s1 = common global i16 0, align 2
@i2 = common global i32 0, align 4 @i2 = common global i32 0, align 4
@i1 = common global i32 0, align 4 @i1 = common global i32 0, align 4
@f2 = common global float 0.000000e+00, align 4 @f2 = common global float 0.000000e+00, align 4
@f1 = common global float 0.000000e+00, align 4 @f1 = common global float 0.000000e+00, align 4
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s -check-prefix=mips32r2 ; RUN: < %s | FileCheck %s -check-prefix=mips32r2
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s -check-prefix=mips32 ; RUN: < %s | FileCheck %s -check-prefix=mips32
@b2 = global i8 0, align 1 @b2 = global i8 0, align 1
@b1 = global i8 1, align 1 @b1 = global i8 1, align 1
@uc1 = global i8 0, align 1 @uc1 = global i8 0, align 1
@uc2 = global i8 -1, align 1 @uc2 = global i8 -1, align 1
@sc1 = global i8 -128, align 1 @sc1 = global i8 -128, align 1
@sc2 = global i8 127, align 1 @sc2 = global i8 127, align 1
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
@s = common global i8* null, align 4 @s = common global i8* null, align 4
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo() #0 { define void @foo() #0 {
entry: entry:
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/logopm.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s
@ub1 = common global i8 0, align 1 @ub1 = common global i8 0, align 1
@ub2 = common global i8 0, align 1 @ub2 = common global i8 0, align 1
@ub3 = common global i8 0, align 1 @ub3 = common global i8 0, align 1
@uc1 = common global i8 0, align 1 @uc1 = common global i8 0, align 1
@uc2 = common global i8 0, align 1 @uc2 = common global i8 0, align 1
@uc3 = common global i8 0, align 1 @uc3 = common global i8 0, align 1
@us1 = common global i16 0, align 2 @us1 = common global i16 0, align 2
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/memtest1.ll

; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s \ ; RUN: -fast-isel-abort=1 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=32R1 ; RUN: -check-prefix=ALL -check-prefix=32R1
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s \ ; RUN: -fast-isel-abort=1 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=32R2 ; RUN: -check-prefix=ALL -check-prefix=32R2
@str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1 @str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1
@src = global i8* getelementptr inbounds ([12 x i8], [12 x i8]* @str, i32 0, i32 0), align 4 @src = global i8* getelementptr inbounds ([12 x i8], [12 x i8]* @str, i32 0, i32 0), align 4
@i = global i32 12, align 4 @i = global i32 12, align 4
@dest = common global [50 x i8] zeroinitializer, align 1 @dest = common global [50 x i8] zeroinitializer, align 1
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1)
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/mul1.ll

; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 \ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic
; RUN: -fast-isel -mips-fast-isel -relocation-model=pic ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 \
; RUN: -fast-isel -mips-fast-isel -relocation-model=pic
; The test is just to make sure it is able to allocate ; The test is just to make sure it is able to allocate
; registers for this example. There was an issue with allocating AC0 ; registers for this example. There was an issue with allocating AC0
; after a mul instruction. ; after a mul instruction.
declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
define i32 @foo(i32 %a, i32 %b) { define i32 @foo(i32 %a, i32 %b) {
entry: entry:
%0 = mul i32 %a, %b %0 = mul i32 %a, %b
%1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %b) %1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %b)
%2 = extractvalue { i32, i1 } %1, 0 %2 = extractvalue { i32, i1 } %1, 0
ret i32 %2 ret i32 %2
} }

llvm/trunk/test/CodeGen/Mips/Fast-ISel/nullvoid.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo() { define void @foo() {
entry: entry:
ret void ret void
; CHECK: jr $ra ; CHECK: jr $ra
} }

llvm/trunk/test/CodeGen/Mips/Fast-ISel/overflt.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@x = common global [128000 x float] zeroinitializer, align 4 @x = common global [128000 x float] zeroinitializer, align 4
@y = global float* getelementptr inbounds ([128000 x float], [128000 x float]* @x, i32 0, i32 0), align 4 @y = global float* getelementptr inbounds ([128000 x float], [128000 x float]* @x, i32 0, i32 0), align 4
@result = common global float 0.000000e+00, align 4 @result = common global float 0.000000e+00, align 4
@.str = private unnamed_addr constant [5 x i8] c"%f \0A\00", align 1 @.str = private unnamed_addr constant [5 x i8] c"%f \0A\00", align 1
; Function Attrs: nounwind ; Function Attrs: nounwind
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/rem1.ll

; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s ; RUN: -fast-isel-abort=1 | FileCheck %s
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
; RUN: -fast-isel=true -mips-fast-isel -fast-isel-abort=1 | FileCheck %s ; RUN: -fast-isel-abort=1 | FileCheck %s
@sj = global i32 200, align 4 @sj = global i32 200, align 4
@sk = global i32 -47, align 4 @sk = global i32 -47, align 4
@uj = global i32 200, align 4 @uj = global i32 200, align 4
@uk = global i32 43, align 4 @uk = global i32 43, align 4
@si = common global i32 0, align 4 @si = common global i32 0, align 4
@ui = common global i32 0, align 4 @ui = common global i32 0, align 4
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/retabi.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@i = global i32 75, align 4 @i = global i32 75, align 4
@s = global i16 -345, align 2 @s = global i16 -345, align 2
@c = global i8 118, align 1 @c = global i8 118, align 1
@f = global float 0x40BE623360000000, align 4 @f = global float 0x40BE623360000000, align 4
@d = global double 1.298330e+03, align 8 @d = global double 1.298330e+03, align 8
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/sel1.ll

; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O2 -relocation-model=pic \ ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O2 -relocation-model=pic \
; RUN: -fast-isel -mips-fast-isel -fast-isel-abort=1 | FileCheck %s ; RUN: -fast-isel -fast-isel-abort=1 | FileCheck %s
define i1 @sel_i1(i1 %j, i1 %k, i1 %l) { define i1 @sel_i1(i1 %j, i1 %k, i1 %l) {
entry: entry:
; CHECK-LABEL: sel_i1: ; CHECK-LABEL: sel_i1:
; FIXME: The following instruction is redundant. ; FIXME: The following instruction is redundant.
; CHECK: xor $[[T0:[0-9]+]], $4, $zero ; CHECK: xor $[[T0:[0-9]+]], $4, $zero
; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]] ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/shftopm.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 \
; RUN: -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s ; RUN: -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 \
; RUN: -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s ; RUN: -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s
@s1 = global i16 -89, align 2 @s1 = global i16 -89, align 2
@s2 = global i16 4, align 2 @s2 = global i16 4, align 2
@us1 = global i16 -503, align 2 @us1 = global i16 -503, align 2
@us2 = global i16 5, align 2 @us2 = global i16 5, align 2
@s3 = common global i16 0, align 2 @s3 = common global i16 0, align 2
@us3 = common global i16 0, align 2 @us3 = common global i16 0, align 2
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/shift.ll

; RUN: llc -march=mipsel -mcpu=mips32r2 -O1 -fast-isel=true -mips-fast-isel -filetype=obj %s -o - \ ; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -fast-isel=true -filetype=obj %s -o - \
; RUN: | llvm-objdump -arch mipsel -mcpu=mips32r2 -d - | FileCheck %s ; RUN: | llvm-objdump -arch mipsel -mcpu=mips32r2 -d - | FileCheck %s
; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used. ; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used.
%struct.s = type { [4 x i8], i32 } %struct.s = type { [4 x i8], i32 }
define i32 @main() nounwind uwtable { define i32 @main() nounwind uwtable {
entry: entry:
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestore.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@abcd = external global i32 @abcd = external global i32
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @foo() { define void @foo() {
entry: entry:
store i32 12345, i32* @abcd, align 4 store i32 12345, i32* @abcd, align 4
; CHECK: addiu $[[REG1:[0-9]+]], $zero, 12345 ; CHECK: addiu $[[REG1:[0-9]+]], $zero, 12345
; CHECK: lw $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}}) ; CHECK: lw $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}})
; CHECK: sw $[[REG1]], 0($[[REG2]]) ; CHECK: sw $[[REG1]], 0($[[REG2]])
ret void ret void
} }

llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s -check-prefix=mips32r2 ; RUN: < %s | FileCheck %s -check-prefix=mips32r2
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s -check-prefix=mips32 ; RUN: < %s | FileCheck %s -check-prefix=mips32
@f = common global float 0.000000e+00, align 4 @f = common global float 0.000000e+00, align 4
@de = common global double 0.000000e+00, align 8 @de = common global double 0.000000e+00, align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @f1() #0 { define void @f1() #0 {
entry: entry:
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llvm/trunk/test/CodeGen/Mips/Fast-ISel/simplestorei.ll

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32 \ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
@ijk = external global i32 @ijk = external global i32
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @si2_1() #0 { define void @si2_1() #0 {
entry: entry:
store i32 32767, i32* @ijk, align 4 store i32 32767, i32* @ijk, align 4
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llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll

; Check that register scavenging spill slot is close to $fp. ; Check that register scavenging spill slot is close to $fp.
; RUN: llc -march=mipsel -O0 < %s | FileCheck %s ; RUN: llc -march=mipsel -O0 -fast-isel=false < %s | FileCheck %s
; CHECK: sw ${{.*}}, 4($sp) ; CHECK: sw ${{.*}}, 8($sp)
; CHECK: lw ${{.*}}, 4($sp) ; CHECK: lw ${{.*}}, 8($sp)
define i32 @main(i32 signext %argc, i8** %argv) "no-frame-pointer-elim"="true" { define i32 @main(i32 signext %argc, i8** %argv) #0 {
entry: entry:
%retval = alloca i32, align 4 %retval = alloca i32, align 4
%argc.addr = alloca i32, align 4 %argc.addr = alloca i32, align 4
%argv.addr = alloca i8**, align 4 %argv.addr = alloca i8**, align 4
%v0 = alloca <16 x i8>, align 16 %v0 = alloca <16 x i8>, align 16
%.compoundliteral = alloca <16 x i8>, align 16 %.compoundliteral = alloca <16 x i8>, align 16
%v1 = alloca <16 x i8>, align 16 %v1 = alloca <16 x i8>, align 16
%.compoundliteral1 = alloca <16 x i8>, align 16 %.compoundliteral1 = alloca <16 x i8>, align 16
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%1 = load <16 x i8>, <16 x i8>* %.compoundliteral1 %1 = load <16 x i8>, <16 x i8>* %.compoundliteral1
store <16 x i8> %1, <16 x i8>* %v1, align 16 store <16 x i8> %1, <16 x i8>* %v1, align 16
%2 = load <16 x i8>, <16 x i8>* %v0, align 16 %2 = load <16 x i8>, <16 x i8>* %v0, align 16
%3 = load <16 x i8>, <16 x i8>* %v1, align 16 %3 = load <16 x i8>, <16 x i8>* %v1, align 16
%mul = mul <16 x i8> %2, %3 %mul = mul <16 x i8> %2, %3
store <16 x i8> %mul, <16 x i8>* %result, align 16 store <16 x i8> %mul, <16 x i8>* %result, align 16
ret i32 0 ret i32 0
} }
attributes #0 = { noinline optnone "no-frame-pointer-elim"="true" }