enable coalescing of COPY and MOVi32imm

[• hulx2000]

Summary

This patch eanble register coalescing to coalesce the following:

  %vreg2<def> = MOVi32imm 1; GPR32:%vreg2
  %W1<def> = COPY %vreg2; GPR32:%vreg2

into:
  %W1<def> = MOVi32imm 1

[t.p.northover]

This looks fine to me.

Tim.

[weimingz]

Committed revision 243033

lib/Target/AArch64/AArch64InstrInfo.cpp

void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
   MRI.constrainRegClass(TrueReg, RC);
   MRI.constrainRegClass(FalseReg, RC);
 
   // Insert the csel.
   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm(
       CC);
 }
 
+/// Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx.
+static bool canBeExpandedToORR(const MachineInstr *MI, unsigned BitSize) {
+  uint64_t Imm = MI->getOperand(1).getImm();
+  uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
+  uint64_t Encoding;
+  return AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding);
+}
+
 // FIXME: this implementation should be micro-architecture dependent, so a
 // micro-architecture target hook should be introduced here in future.
 bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr *MI) const {
   if (!Subtarget.isCortexA57() && !Subtarget.isCortexA53())
     return MI->isAsCheapAsAMove();
 
   switch (MI->getOpcode()) {
   default:
bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr *MI) const {
   case AArch64::EONXrr:
   case AArch64::EORWrr:
   case AArch64::EORXrr:
   case AArch64::ORNWrr:
   case AArch64::ORNXrr:
   case AArch64::ORRWrr:
   case AArch64::ORRXrr:
     return true;
+  // If MOVi32imm or MOVi64imm can be expanded into ORRWri or
+  // ORRXri, it is as cheap as MOV
+  case AArch64::MOVi32imm:
+    return canBeExpandedToORR(MI, 32);
+  case AArch64::MOVi64imm:
+    return canBeExpandedToORR(MI, 64);
   }
 
   llvm_unreachable("Unknown opcode to check as cheap as a move!");
 }
 
 bool AArch64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
                                              unsigned &SrcReg, unsigned &DstReg,
                                              unsigned &SubIdx) const {

test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll

+; RUN: llc < %s | FileCheck %s
+
+; CHECK:        orr     w0, wzr, #0x1
+; CHECK-NEXT :  bl      foo
+; CHECK-NEXT :  orr     w0, wzr, #0x1
+; CHECK-NEXT :  bl      foo
+
+target triple = "aarch64--linux-android"
+declare i32 @foo(i32)
+
+; Function Attrs: nounwind uwtable
+define i32 @main() {
+entry:
+  %call = tail call i32 @foo(i32 1)
+  %call1 = tail call i32 @foo(i32 1)
+  ret i32 0
+}
+