[mips][micromips] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions

[hvarga]

Summary

The patch implements microMIPSr6 ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions.

[dsanders]

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

1718–1720

Nit: Indentation

1721–1724

Nit: Use ternary operator

lib/Target/Mips/MicroMips32r6InstrFormats.td

294

Style nit: rd is normally first.

lib/Target/Mips/MicroMips32r6InstrInfo.td

287–291

There's several issues here:

• This class belongs in MicroMips32r6InstrFormats.td similar to MipsR6Inst in Mips32r6InstrFormats.td and the formats (*_FM) should inherit from it, not the descriptions (*_DESC)
• Don't use Predicates directly. Inherit from PredicateControl and use its fields.
• DecoderNamespace is a property of the format/encoding and not of the description.
• HasStdEnc is a predicate of the format/encoding and belongs in the EncodingPredicates member of the format, but ...
  • ... HasStdEnc means not microMIPS and not MIPS16. It's not correct to use it for microMIPS.
• Use ISA_MICROMIPS32R6 on the def since it's a property of the instruction and not the description. Also it's more consistent with the other instructions.
  • I see you've already have ISA_MICROMIPS32R6 on the instructions. The reason the adjective isn't working there is because you aren't using PredicateControl and/or you overrode Predicates.

[hvarga]

Modified patch according the comments from dsanders.

[dsanders]

LGTM with some minor changes

lib/Target/Mips/MicroMips32r6InstrInfo.td

287–301

The *_FM should inherit fro MicroMipsR6Inst16 rather than the *_DESC
Also, Indentation.

lib/Target/Mips/MicroMipsInstrFormats.td

40–45 ↗

(On Diff #33422)

Please define this with the other adjectives in MipsInstrInfo.td and follow the naming convention used by the others (e.g. ISA_MICROMIPS_NOT_32R6_64R6)

lib/Target/Mips/MicroMipsInstrInfo.td

556–558

Indentation

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
                                     uint64_t Address,
                                     const void *Decoder);
 
 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
                                   unsigned Value,
                                   uint64_t Address,
                                   const void *Decoder);
 
+static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
+                                  unsigned Value,
+                                  uint64_t Address,
+                                  const void *Decoder);
+
 static DecodeStatus DecodeSimm4(MCInst &Inst,
                                 unsigned Value,
                                 uint64_t Address,
                                 const void *Decoder);
 
 static DecodeStatus DecodeSimm16(MCInst &Inst,
                                  unsigned Insn,
                                  uint64_t Address,
DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
                                               raw_ostream &VStream,
                                               raw_ostream &CStream) const {
   uint32_t Insn;
   DecodeStatus Result;
 
   if (IsMicroMips) {
     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 
+    if (hasMips32r6()) {
+      DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
+      // Calling the auto-generated decoder function.
+      Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, Address,
+                                 this, STI);
+    } else {
       DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
       // Calling the auto-generated decoder function.
       Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
                                this, STI);
+    }
+
     if (Result != MCDisassembler::Fail) {
       Size = 2;
       return Result;
     }
 
     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
     if (Result == MCDisassembler::Fail)
       return MCDisassembler::Fail;
static DecodeStatus DecodeLiSimm7(MCInst &Inst,
                                   const void *Decoder) {
   if (Value == 0x7F)
     Inst.addOperand(MCOperand::createImm(-1));
   else
     Inst.addOperand(MCOperand::createImm(Value));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
+                                  unsigned Value,
+                                  uint64_t Address,
+                                  const void *Decoder) {
+  if (Value == 0x0)
+    Inst.addOperand(MCOperand::createImm(8));
+  else
+    Inst.addOperand(MCOperand::createImm(Value));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeSimm4(MCInst &Inst,
                                 unsigned Value,
                                 uint64_t Address,
                                 const void *Decoder) {
   Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
   return MCDisassembler::Success;
 }
 

lib/Target/Mips/MicroMips32r6InstrFormats.td

class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
 
   let Inst{31-26} = 0;
   let Inst{25-21} = rd;
   let Inst{20-16} = rt;
   let Inst{15-11} = shamt;
   let Inst{10}    = rotate;
   let Inst{9-0}   = funct;
 }
+
+class POOL16A_ADDU16_FM_MMR6 {
+  bits<3> rs;
+  bits<3> rt;
+  bits<3> rd;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = 0b000001;
+  let Inst{9-7}   = rs;
+  let Inst{6-4}   = rt;
+  let Inst{3-1}   = rd;
+  let Inst{0}     = 0;
+}
+
+class POOL16C_AND16_FM_MMR6 {
+  bits<3> rt;
+  bits<3> rs;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = 0b010001;
+  let Inst{9-7}   = rt;
+  let Inst{6-4}   = rs;
+  let Inst{3-0}   = 0b0001;
+}
+
+class POOL16C_NOT16_FM_MMR6 {
+  bits<3> rt;
+  bits<3> rs;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = 0x11;
+  let Inst{9-7}   = rt;
+  let Inst{6-4}   = rs;
+  let Inst{3-0}   = 0b0000;
+}
+
+class POOL16C_OR16_FM_MMR6 {
+  bits<3> rt;
+  bits<3> rs;
+
+  bits<16> Inst;
+
+  let Inst{15-10} = 0b010001;
+  let Inst{9-7}   = rt;
+  let Inst{6-4}   = rs;
+  let Inst{3-0}   = 0b1001;
+}

lib/Target/Mips/MicroMips32r6InstrInfo.td

 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
 class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
+class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
+class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
+class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>;
+class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
+class OR16_MMR6_ENC : POOL16C_OR16_FM_MMR6;
+class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>;
+class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>;
 
 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
                                   RegisterOperand GPROpnd>
     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
   dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
   dag OutOperandList = (outs);
   string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
   list<Register> Defs = [AT];

 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;
 class ORI_MMR6_DESC : ArithLogicI<"ori", simm16, GPR32Opnd>;
 class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>;
 class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>;
 
+// Class used for microMIPS32r6 and microMIPS64r6 instructions.
+class MicroMipsR6Inst16 {
+  string DecoderNamespace = "MicroMipsR6";
+  list<Predicate> Predicates = [HasStdEnc, HasMicroMips32r6];
+}
+
+class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
+  MMR6Arch<"addu16">, MicroMipsR6Inst16;
+class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
+  MMR6Arch<"and16">, MicroMipsR6Inst16;
+class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
+  MMR6Arch<"andi16">, MicroMipsR6Inst16;
+class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">,
+  MicroMipsR6Inst16;
+class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
+  MMR6Arch<"or16">, MicroMipsR6Inst16;
+class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
+  MMR6Arch<"sll16">, MicroMipsR6Inst16;
+class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
+  MMR6Arch<"srl16">, MicroMipsR6Inst16;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
 def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
                   ISA_MICROMIPS32R6;
 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
                   ISA_MICROMIPS32R6;
 def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
+def ADDU16_MMR6 : StdMMR6Rel, ADDU16_MMR6_DESC, ADDU16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def AND16_MMR6 : StdMMR6Rel, AND16_MMR6_DESC, AND16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def ANDI16_MMR6 : StdMMR6Rel, ANDI16_MMR6_DESC, ANDI16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def NOT16_MMR6 : StdMMR6Rel, NOT16_MMR6_DESC, NOT16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def OR16_MMR6 : StdMMR6Rel, OR16_MMR6_DESC, OR16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def SLL16_MMR6 : StdMMR6Rel, SLL16_MMR6_DESC, SLL16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
+def SRL16_MMR6 : StdMMR6Rel, SRL16_MMR6_DESC, SRL16_MMR6_ENC,
+                  ISA_MICROMIPS32R6;
 }
 
 //===----------------------------------------------------------------------===//
 //
 // MicroMips instruction aliases
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsInstAlias<"ei", (EI_MMR6 ZERO), 1>, ISA_MICROMIPS32R6;
 def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;

lib/Target/Mips/MicroMipsInstrInfo.td

 
 def simm9_addiusp : Operand<i32> {
   let EncoderMethod = "getSImm9AddiuspValue";
   let DecoderMethod = "DecodeSimm9SP";
 }
 
 def uimm3_shift : Operand<i32> {
   let EncoderMethod = "getUImm3Mod8Encoding";
+  let DecoderMethod = "DecodePOOL16BEncodedField";
 }
 
 def simm3_lsa2 : Operand<i32> {
   let EncoderMethod = "getSImm3Lsa2Value";
   let DecoderMethod = "DecodeAddiur2Simm7";
 }
 
 def uimm4_andi : Operand<i32> {
class UncondBranchMM16<string opstr> :
   let isBranch = 1;
   let isTerminator = 1;
   let isBarrier = 1;
   let hasDelaySlot = 1;
   let Predicates = [RelocPIC, InMicroMips];
   let Defs = [AT];
 }
 
 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
                 ARITH_FM_MM16<0>;
 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
                 ARITH_FM_MM16<1>;
 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>;
 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
                LOGIC_FM_MM16<0x2>;
 def OR16_MM  : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
                LOGIC_FM_MM16<0x3>;
 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
                LOGIC_FM_MM16<0x1>;

test/MC/Disassembler/Mips/micromips32r6.txt

 0x00 0xa4 0x1b 0x10 # CHECK: xor $3, $4, $5
 
 0x70 0x64 0x04 0xd2 # CHECK: xori $3, $4, 1234
 
 0x00 0x64 0x2b 0x3c # CHECK: seb $3, $4
 
 0x00 0x64 0x3b 0x3c # CHECK: seh $3, $4
 
+0x04 0xcc # CHECK: addu16 $6, $17, $4
+
+0x44 0x21 # CHECK: and16 $16, $2
+
+0x2e 0x56 # CHECK: andi16 $4, $5, 8
+
+0x46 0x70 # CHECK: not16 $4, $7
+
+0x45 0xf9 # CHECK: or16 $3, $7
+
+0x25 0xe0 # CHECK: sll16 $3, $6, 8
+
+0x25 0xe1 # CHECK: srl16 $3, $6, 8
+

test/MC/Disassembler/Mips/micromips64r6.txt

 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r6 -mattr=micromips | FileCheck %s
 
 0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5
 
 0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4
 
 0x42 0x03 0x00 0x04 # CHECK: dati $3, 4
 
 0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7
 
 0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 7
 
 0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 3, 7
 
 0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5
+
+0x04 0xcc # CHECK: addu16 $6, $17, $4
+
+0x44 0x21 # CHECK: and16 $16, $2
+
+0x2e 0x56 # CHECK: andi16 $4, $5, 8
+
+0x46 0x70 # CHECK: not16 $4, $7
+
+0x45 0xf9 # CHECK: or16 $3, $7
+
+0x25 0xe0 # CHECK: sll16 $3, $6, 8
+
+0x25 0xe1 # CHECK: srl16 $3, $6, 8

test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   seh $3, $4               # CHECK: seh $3, $4          # encoding: [0x00,0x64,0x3b,0x3c]
   seleqz $2,$3,$4          # CHECK: seleqz $2, $3, $4   # encoding: [0x00,0x83,0x11,0x40]
   selnez $2,$3,$4          # CHECK: selnez $2, $3, $4   # encoding: [0x00,0x83,0x11,0x80]
   sll $4, $3, 7            # CHECK: sll $4, $3, 7       # encoding: [0x00,0x83,0x38,0x00]
   sub $3, $4, $5           # CHECK: sub $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x90]
   subu $3, $4, $5          # CHECK: subu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0xd0]
   xor $3, $4, $5           # CHECK: xor $3, $4, $5      # encoding: [0x00,0xa4,0x1b,0x10]
   xori $3, $4, 1234        # CHECK: xori $3, $4, 1234   # encoding: [0x70,0x64,0x04,0xd2]
+  addu16 $6, $17, $4       # CHECK: addu16 $6, $17, $4  # encoding: [0x04,0xcc]
+  and16 $16, $2            # CHECK: and16 $16, $2       # encoding: [0x44,0x21]
+  andi16 $4, $5, 8         # CHECK: andi16 $4, $5, 8    # encoding: [0x2e,0x56]
+  not16 $4, $7             # CHECK: not16 $4, $7        # encoding: [0x46,0x70]
+  or16 $3, $7              # CHECK: or16 $3, $7         # encoding: [0x45,0xf9]
+  sll16 $3, $6, 8          # CHECK: sll16 $3, $6, 8     # encoding: [0x25,0xe0]
+  srl16 $3, $6, 8          # CHECK: srl16 $3, $6, 8     # encoding: [0x25,0xe1]
 

test/MC/Mips/micromips64r6/valid.s

 # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 -mattr=micromips | FileCheck %s
 a:
         .set noat
         daui $3, $4, 5           # CHECK: daui $3, $4, 5        # encoding: [0xf0,0x64,0x00,0x05]
         dahi $3, 4               # CHECK: dahi $3, 4            # encoding: [0x42,0x23,0x00,0x04]
         dati $3, 4               # CHECK: dati $3, 4            # encoding: [0x42,0x03,0x00,0x04]
         dext $9, $6, 3, 7        # CHECK: dext $9, $6, 3, 7     # encoding: [0x59,0x26,0x30,0xec]
         dextm $9, $6, 3, 7       # CHECK: dextm $9, $6, 3, 7    # encoding: [0x59,0x26,0x30,0xe4]
         dextu $9, $6, 3, 7       # CHECK: dextu $9, $6, 3, 7    # encoding: [0x59,0x26,0x30,0xd4]
         dalign $4, $2, $3, 5     # CHECK: dalign $4, $2, $3, 5  # encoding: [0x58,0x43,0x25,0x1c]
+        addu16 $6, $17, $4       # CHECK: addu16 $6, $17, $4    # encoding: [0x04,0xcc]
+        and16 $16, $2            # CHECK: and16 $16, $2         # encoding: [0x44,0x21]
+        andi16 $4, $5, 8         # CHECK: andi16 $4, $5, 8      # encoding: [0x2e,0x56]
+        not16 $4, $7             # CHECK: not16 $4, $7          # encoding: [0x46,0x70]
+        or16 $3, $7              # CHECK: or16 $3, $7         # encoding: [0x45,0xf9]
+        sll16 $3, $6, 8          # CHECK: sll16 $3, $6, 8     # encoding: [0x25,0xe0]
+        srl16 $3, $6, 8          # CHECK: srl16 $3, $6, 8     # encoding: [0x25,0xe1]
 
 1: