FastISel support for instructions that load floating point immediate values.

[sunfish]

Summary

This patch adds FastISel support for instructions which have a floating point immediate operand and no other input operands, and a register output.

[echristo]

I assume for use in WebAssembly? Any hope of a backend test for that?

-eric

[sunfish]

Yes, this is for WebAssembly. This can wait if you want a testcase to accompany it directly, otherwise we'll add a testcase when we add the WebAssembly code which uses this.

[echristo]

It'd be nice if it isn't going to make things unduly complicated for you.

-eric

[sunfish]

Ok. It's not too complicated. I'll postpone these for now.

include/llvm/CodeGen/FastISel.h

                             const TargetRegisterClass *RC, unsigned Op0,
                             bool Op0IsKill, uint64_t Imm1, uint64_t Imm2);
 
+  /// \brief Emit a MachineInstr with a floating-point immediate and a result
+  /// register in the given register class.
+  unsigned fastEmitInst_f(unsigned MachineInstOpcode,
+                          const TargetRegisterClass *RC,
+                          const ConstantFP *FPImm);
+
   /// \brief Emit a MachineInstr with two register operands and a result
   /// register in the given register class.
   unsigned fastEmitInst_rf(unsigned MachineInstOpcode,

lib/CodeGen/SelectionDAG/FastISel.cpp

   return ResultReg;
 }
 
+unsigned FastISel::fastEmitInst_f(unsigned MachineInstOpcode,
+                                  const TargetRegisterClass *RC,
+                                  const ConstantFP *FPImm) {
+  const MCInstrDesc &II = TII.get(MachineInstOpcode);
+
+  unsigned ResultReg = createResultReg(RC);
+
+  if (II.getNumDefs() >= 1)
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
+        .addFPImm(FPImm);
+  else {
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
+        .addFPImm(FPImm);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+            TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+  }
+  return ResultReg;
+}
+
 unsigned FastISel::fastEmitInst_rf(unsigned MachineInstOpcode,
                                    const TargetRegisterClass *RC, unsigned Op0,
                                    bool Op0IsKill, const ConstantFP *FPImm) {