[mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.

[Kai]

Summary

Hi Daniel,

Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor. E.g. dmtc2 rt,0x4057 starts calculation of sha-1.

I had to introduce a new deconding namespace to avoid a decoding conflict.

Regards,
Kai

[Kai]

Forgot to commit the latest test case changes.

[dsanders]

LGTM with a nit.

Just to check: Is the decoder conflict something that happens now (I couldn't reproduce it) or are you accounting for MIPS64 dmfc2/dmtc2's conflicting when they are added?

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

897 ↗

(On Diff #26662)

Nit: Indentation, should line up with the 'D' in DecoderTableCnMips32.

[Kai]

The decoder conflict happens now. I had to explicitly add the DecoderNamespace to get rid of it.

[dsanders]

Hmm. I can easily see where the decoder conflict should be but for some reason tablegen isn't reporting it in my build when I delete the explicit DecoderNamespace (and comment out the references to the undefined table this causes).

In any case, your patch is correct. Feel free to commit.

[dsanders]

I think I see what's happening in my build. It seems tablegen only complains about decoder conflicts when the mask of literal bits and the values of those masked bits are exactly the same. In the case of DMFC2 vs DMFC2_OCTEON we have:

DMFC2        01001000001_____ _____00000000___
DMFC2_OCTEON 01001000001_____ ________________

So instead of reporting decoder conflicts as an error it quietly prefers DMFC2 when bits 10 down to 3 are 0, and therefore disassembles incorrectly for the CnMips case.

llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

public:
   bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
   bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
   bool hasMips32r6() const {
     return STI.getFeatureBits()[Mips::FeatureMips32r6];
   }
 
   bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
 
+  bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
+
   bool hasCOP3() const {
     // Only present in MIPS-I and MIPS-II
     return !hasMips32() && !hasMips3();
   }
 
   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
                               ArrayRef<uint8_t> Bytes, uint64_t Address,
                               raw_ostream &VStream,
if (hasMips32r6()) {
     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
                                Address, this, STI);
     if (Result != MCDisassembler::Fail) {
       Size = 4;
       return Result;
     }
   }
 
+  if (hasCnMips()) {
+    DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
+    Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
+                               Address, this, STI);
+    if (Result != MCDisassembler::Fail) {
+      Size = 4;
+      return Result;
+    }
+  }
+
   if (isGP64()) {
     DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
     Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
                                Address, this, STI);
     if (Result != MCDisassembler::Fail) {
       Size = 4;
       return Result;
     }

llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td

 // explanation.
 
 // Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
 // where %PART may be %hi or %lo, depending on the relocation kind
 // that $tgt is annotated with.
 def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
   (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
 
-// Cavium Octeon cmMIPS instructions
-let EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
+// Cavium Octeon cnMIPS instructions
+let DecoderNamespace = "CnMips",
+    EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
     AdditionalPredicates = [HasCnMips] in {
 
 class Count1s<string opstr, RegisterOperand RO>:
   InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
          [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
   let TwoOperandAliasConstraint = "$rd = $rs";
 }
 
InstSE<(outs), (ins RO:$rs, uimm5_64:$p, opnd:$offset),
          [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
                   bb:$offset)], IIBranch, FrmI, opstr> {
   let isBranch = 1;
   let isTerminator = 1;
   let hasDelaySlot = 1;
   let Defs = [AT];
 }
 
+class MFC2OP<string asmstr, RegisterOperand RO> :
+  InstSE<(outs RO:$rt, uimm16:$imm16), (ins),
+         !strconcat(asmstr, "\t$rt, $imm16"), [], NoItinerary, FrmFR>;
+
 // Unsigned Byte Add
 let Pattern = [(set GPR64Opnd:$rd,
                     (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
 def BADDu  : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
                               ADD_FM<0x1c, 0x28>;
 
 // Branch on Bit Clear /+32
 def BBIT0  : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd>, BBIT_FM<0x32>;

 def VMM0  : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
                                 ADD_FM<0x1c, 0x10>;
 
 // 64-bit Unsigned Multiply and Add
 let Defs = [MPL1, MPL2, P0, P1, P2] in
 def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
                                  ADD_FM<0x1c, 0x0f>;
 
+// Move between CPU and coprocessor registers
+def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>;
+def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>;
 }
 
 }
 
 /// Move between CPU and coprocessor registers
 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
 def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;

llvm/trunk/lib/Target/Mips/MipsInstrFormats.td

class MFC3OP_FM<bits<6> op, bits<5> mfmt>
   let Inst{31-26} = op;
   let Inst{25-21} = mfmt;
   let Inst{20-16} = rt;
   let Inst{15-11} = rd;
   let Inst{10-3}  = 0;
   let Inst{2-0}   = sel;
 }
 
+class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
+  bits<5>  rt;
+  bits<16> imm16;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = op;
+  let Inst{25-21} = mfmt;
+  let Inst{20-16} = rt;
+  let Inst{15-0}  = imm16;
+}
+
 class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
   bits<5> rd;
   bits<5> rs;
   bits<5> rt;
 
   bits<32> Inst;
 
   let Inst{31-26} = op;

llvm/trunk/test/MC/Mips/octeon-instructions.s

 # CHECK: bbit132 $24, 10, foo         # encoding: [0xfb,0x0a,A,A]
 # CHECK: bbit132 $14, 14, foo         # encoding: [0xf9,0xce,A,A]
 # CHECK: cins  $25, $10, 22, 2        # encoding: [0x71,0x59,0x15,0xb2]
 # CHECK: cins  $9, $9, 17, 29         # encoding: [0x71,0x29,0xec,0x72]
 # CHECK: cins32 $15, $2, 18, 8        # encoding: [0x70,0x4f,0x44,0xb3]
 # CHECK: cins32 $22, $22, 9, 22       # encoding: [0x72,0xd6,0xb2,0x73]
 # CHECK: cins32 $24, $ra, 0, 31       # encoding: [0x73,0xf8,0xf8,0x33]
 # CHECK: cins32 $15, $15, 5, 5        # encoding: [0x71,0xef,0x29,0x73]
+# CHECK: dmtc2 $2, 16455              # encoding: [0x48,0xa2,0x40,0x47]
+# CHECK: dmfc2 $2, 64                 # encoding: [0x48,0x22,0x00,0x40]
 # CHECK: dmul  $9, $6, $7             # encoding: [0x70,0xc7,0x48,0x03]
 # CHECK: dmul  $19, $24, $25          # encoding: [0x73,0x19,0x98,0x03]
 # CHECK: dmul  $9, $9, $6             # encoding: [0x71,0x26,0x48,0x03]
 # CHECK: dmul  $21, $21, $25          # encoding: [0x72,0xb9,0xa8,0x03]
 # CHECK: dpop  $9, $6                 # encoding: [0x70,0xc0,0x48,0x2d]
 # CHECK: dpop  $15, $22               # encoding: [0x72,0xc0,0x78,0x2d]
 # CHECK: dpop  $12, $12               # encoding: [0x71,0x80,0x60,0x2d]
 # CHECK: exts  $4, $25, 27, 15        # encoding: [0x73,0x24,0x7e,0xfa]
foo:
   bbit132 $24, 10, foo
   bbit1 $14, 46, foo
   cins  $25, $10, 22, 2
   cins  $9, 17, 29
   cins32 $15, $2, 18, 8
   cins32 $22, 9, 22
   cins  $24, $31, 32, 31
   cins  $15, 37, 5
+  dmtc2 $2, 0x4047
+  dmfc2 $2, 0x0040
   dmul  $9, $6, $7
   dmul  $19, $24, $25
   dmul  $9, $6
   dmul  $21, $25
   dpop  $9, $6
   dpop  $15, $22
   dpop  $12
   exts  $4, $25, 27, 15