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rotaterightrotateright
committedOct 19, 2019
[MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests); NFC
Patch by: @JoanLluch (Joan LLuch) Differential Revision: https://reviews.llvm.org/D69099 llvm-svn: 375345
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llvmorg-21-initllvmorg-10.0.0-rc1
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‎llvm/test/CodeGen/MSP430/shift-amount-threshold.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=msp430-- < %s | FileCheck %s
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define i16 @testSimplifySetCC_0(i16 %a) {
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; CHECK-LABEL: testSimplifySetCC_0:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: and #32, r12
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; CHECK-NEXT: clrc
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; CHECK-NEXT: rrc r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: ret
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entry:
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%and = and i16 %a, 32
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%cmp = icmp ne i16 %and, 0
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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define i16 @testSimplifySetCC_1(i16 %a) {
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; CHECK-LABEL: testSimplifySetCC_1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: and #32, r12
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; CHECK-NEXT: clrc
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; CHECK-NEXT: rrc r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: ret
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entry:
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%and = and i16 %a, 32
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%cmp = icmp eq i16 %and, 32
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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define i16 @testSiymplifySelect(i16 %a) {
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; CHECK-LABEL: testSiymplifySelect:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: mov r12, r13
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; CHECK-NEXT: clr r12
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; CHECK-NEXT: bit #2048, r13
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; CHECK-NEXT: jeq .LBB2_2
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; CHECK-NEXT: ; %bb.1: ; %entry
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; CHECK-NEXT: mov #3, r12
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; CHECK-NEXT: .LBB2_2: ; %entry
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; CHECK-NEXT: ret
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entry:
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%and = and i16 %a, 2048
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%cmp = icmp eq i16 %and, 0
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%cond = select i1 %cmp, i16 0, i16 3
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ret i16 %cond
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}
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define i16 @testExtendSignBit(i16 %a) {
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; CHECK-LABEL: testExtendSignBit:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: inv r12
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; CHECK-NEXT: swpb r12
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; CHECK-NEXT: mov.b r12, r12
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; CHECK-NEXT: clrc
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; CHECK-NEXT: rrc r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp sgt i16 %a, -1
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%cond = select i1 %cmp, i16 1, i16 0
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ret i16 %cond
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}
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define i16 @testShiftAnd_0(i16 %a) {
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; CHECK-LABEL: testShiftAnd_0:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: swpb r12
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; CHECK-NEXT: sxt r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp slt i16 %a, 0
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%cond = select i1 %cmp, i16 -1, i16 0
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ret i16 %cond
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}
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define i16 @testShiftAnd_1(i16 %a) {
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; CHECK-LABEL: testShiftAnd_1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: swpb r12
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; CHECK-NEXT: mov.b r12, r12
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; CHECK-NEXT: clrc
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; CHECK-NEXT: rrc r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp slt i16 %a, 0
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%cond = select i1 %cmp, i16 1, i16 0
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ret i16 %cond
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}
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define i16 @testShiftAnd_2(i16 %a) {
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; CHECK-LABEL: testShiftAnd_2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: swpb r12
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; CHECK-NEXT: mov.b r12, r12
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; CHECK-NEXT: clrc
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; CHECK-NEXT: rrc r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: and #2, r12
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp slt i16 %a, 0
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%cond = select i1 %cmp, i16 2, i16 0
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ret i16 %cond
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}
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define i16 @testShiftAnd_3(i16 %a) {
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; CHECK-LABEL: testShiftAnd_3:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: swpb r12
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; CHECK-NEXT: sxt r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: and #3, r12
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp slt i16 %a, 0
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%cond = select i1 %cmp, i16 3, i16 0
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ret i16 %cond
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}
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define i16 @testShiftAnd_4(i16 %a, i16 %b) {
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; CHECK-LABEL: testShiftAnd_4:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: mov r12, r14
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; CHECK-NEXT: mov #1, r12
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; CHECK-NEXT: cmp r14, r13
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; CHECK-NEXT: jl .LBB8_2
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; CHECK-NEXT: ; %bb.1: ; %entry
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; CHECK-NEXT: clr r12
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; CHECK-NEXT: .LBB8_2: ; %entry
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; CHECK-NEXT: add r12, r12
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; CHECK-NEXT: add r12, r12
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; CHECK-NEXT: add r12, r12
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; CHECK-NEXT: add r12, r12
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; CHECK-NEXT: add r12, r12
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp sgt i16 %a, %b
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%cond = select i1 %cmp, i16 32, i16 0
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ret i16 %cond
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}

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