@@ -183,17 +183,17 @@ class SILoadStoreOptimizer : public MachineFunctionPass {
183
183
MachineBasicBlock::iterator mergeBufferStorePair (CombineInfo &CI);
184
184
185
185
void updateBaseAndOffset (MachineInstr &I, unsigned NewBase,
186
- int32_t NewOffset);
187
- unsigned computeBase (MachineInstr &MI, const MemAddress &Addr);
188
- MachineOperand createRegOrImm (int32_t Val, MachineInstr &MI);
189
- Optional<int32_t > extractConstOffset (const MachineOperand &Op);
190
- void processBaseWithConstOffset (const MachineOperand &Base, MemAddress &Addr);
186
+ int32_t NewOffset) const ;
187
+ unsigned computeBase (MachineInstr &MI, const MemAddress &Addr) const ;
188
+ MachineOperand createRegOrImm (int32_t Val, MachineInstr &MI) const ;
189
+ Optional<int32_t > extractConstOffset (const MachineOperand &Op) const ;
190
+ void processBaseWithConstOffset (const MachineOperand &Base, MemAddress &Addr) const ;
191
191
// / Promotes constant offset to the immediate by adjusting the base. It
192
192
// / tries to use a base from the nearby instructions that allows it to have
193
193
// / a 13bit constant offset which gets promoted to the immediate.
194
194
bool promoteConstantOffsetToImm (MachineInstr &CI,
195
195
MemInfoMap &Visited,
196
- SmallPtrSet<MachineInstr *, 4 > &Promoted);
196
+ SmallPtrSet<MachineInstr *, 4 > &Promoted) const ;
197
197
198
198
public:
199
199
static char ID;
@@ -1151,7 +1151,7 @@ SILoadStoreOptimizer::mergeBufferStorePair(CombineInfo &CI) {
1151
1151
}
1152
1152
1153
1153
MachineOperand
1154
- SILoadStoreOptimizer::createRegOrImm (int32_t Val, MachineInstr &MI) {
1154
+ SILoadStoreOptimizer::createRegOrImm (int32_t Val, MachineInstr &MI) const {
1155
1155
APInt V (32 , Val, true );
1156
1156
if (TII->isInlineConstant (V))
1157
1157
return MachineOperand::CreateImm (Val);
@@ -1168,7 +1168,7 @@ SILoadStoreOptimizer::createRegOrImm(int32_t Val, MachineInstr &MI) {
1168
1168
1169
1169
// Compute base address using Addr and return the final register.
1170
1170
unsigned SILoadStoreOptimizer::computeBase (MachineInstr &MI,
1171
- const MemAddress &Addr) {
1171
+ const MemAddress &Addr) const {
1172
1172
MachineBasicBlock *MBB = MI.getParent ();
1173
1173
MachineBasicBlock::iterator MBBI = MI.getIterator ();
1174
1174
DebugLoc DL = MI.getDebugLoc ();
@@ -1227,13 +1227,13 @@ unsigned SILoadStoreOptimizer::computeBase(MachineInstr &MI,
1227
1227
// Update base and offset with the NewBase and NewOffset in MI.
1228
1228
void SILoadStoreOptimizer::updateBaseAndOffset (MachineInstr &MI,
1229
1229
unsigned NewBase,
1230
- int32_t NewOffset) {
1230
+ int32_t NewOffset) const {
1231
1231
TII->getNamedOperand (MI, AMDGPU::OpName::vaddr)->setReg (NewBase);
1232
1232
TII->getNamedOperand (MI, AMDGPU::OpName::offset)->setImm (NewOffset);
1233
1233
}
1234
1234
1235
1235
Optional<int32_t >
1236
- SILoadStoreOptimizer::extractConstOffset (const MachineOperand &Op) {
1236
+ SILoadStoreOptimizer::extractConstOffset (const MachineOperand &Op) const {
1237
1237
if (Op.isImm ())
1238
1238
return Op.getImm ();
1239
1239
@@ -1259,7 +1259,7 @@ SILoadStoreOptimizer::extractConstOffset(const MachineOperand &Op) {
1259
1259
// %Base:vreg_64 =
1260
1260
// REG_SEQUENCE %LO:vgpr_32, %subreg.sub0, %HI:vgpr_32, %subreg.sub1
1261
1261
void SILoadStoreOptimizer::processBaseWithConstOffset (const MachineOperand &Base,
1262
- MemAddress &Addr) {
1262
+ MemAddress &Addr) const {
1263
1263
if (!Base.isReg ())
1264
1264
return ;
1265
1265
@@ -1314,7 +1314,7 @@ void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base
1314
1314
bool SILoadStoreOptimizer::promoteConstantOffsetToImm (
1315
1315
MachineInstr &MI,
1316
1316
MemInfoMap &Visited,
1317
- SmallPtrSet<MachineInstr *, 4 > &AnchorList) {
1317
+ SmallPtrSet<MachineInstr *, 4 > &AnchorList) const {
1318
1318
1319
1319
if (!(MI.mayLoad () ^ MI.mayStore ()))
1320
1320
return false ;
0 commit comments