-
Notifications
You must be signed in to change notification settings - Fork 12.7k
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
[ARM] Fix for MVE load/store stack accesses
MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices. Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used. Differential Revision: https://reviews.llvm.org/D67327 llvm-svn: 372114
- llvmorg-21-init
- llvmorg-20.1.0-rc2
- llvmorg-20.1.0-rc1
- llvmorg-20-init
- llvmorg-19.1.7
- llvmorg-19.1.6
- llvmorg-19.1.5
- llvmorg-19.1.4
- llvmorg-19.1.3
- llvmorg-19.1.2
- llvmorg-19.1.1
- llvmorg-19.1.0
- llvmorg-19.1.0-rc4
- llvmorg-19.1.0-rc3
- llvmorg-19.1.0-rc2
- llvmorg-19.1.0-rc1
- llvmorg-19-init
- llvmorg-18.1.8
- llvmorg-18.1.7
- llvmorg-18.1.6
- llvmorg-18.1.5
- llvmorg-18.1.4
- llvmorg-18.1.3
- llvmorg-18.1.2
- llvmorg-18.1.1
- llvmorg-18.1.0
- llvmorg-18.1.0-rc4
- llvmorg-18.1.0-rc3
- llvmorg-18.1.0-rc2
- llvmorg-18.1.0-rc1
- llvmorg-18-init
- llvmorg-17.0.6
- llvmorg-17.0.5
- llvmorg-17.0.4
- llvmorg-17.0.3
- llvmorg-17.0.2
- llvmorg-17.0.1
- llvmorg-17.0.0
- llvmorg-17.0.0-rc4
- llvmorg-17.0.0-rc3
- llvmorg-17.0.0-rc2
- llvmorg-17.0.0-rc1
- llvmorg-17-init
- llvmorg-16.0.6
- llvmorg-16.0.5
- llvmorg-16.0.4
- llvmorg-16.0.3
- llvmorg-16.0.2
- llvmorg-16.0.1
- llvmorg-16.0.0
- llvmorg-16.0.0-rc4
- llvmorg-16.0.0-rc3
- llvmorg-16.0.0-rc2
- llvmorg-16.0.0-rc1
- llvmorg-16-init
- llvmorg-15.0.7
- llvmorg-15.0.6
- llvmorg-15.0.5
- llvmorg-15.0.4
- llvmorg-15.0.3
- llvmorg-15.0.2
- llvmorg-15.0.1
- llvmorg-15.0.0
- llvmorg-15.0.0-rc3
- llvmorg-15.0.0-rc2
- llvmorg-15.0.0-rc1
- llvmorg-15-init
- llvmorg-14.0.6
- llvmorg-14.0.5
- llvmorg-14.0.4
- llvmorg-14.0.3
- llvmorg-14.0.2
- llvmorg-14.0.1
- llvmorg-14.0.0
- llvmorg-14.0.0-rc4
- llvmorg-14.0.0-rc3
- llvmorg-14.0.0-rc2
- llvmorg-14.0.0-rc1
- llvmorg-14-init
- llvmorg-13.0.1
- llvmorg-13.0.1-rc3
- llvmorg-13.0.1-rc2
- llvmorg-13.0.1-rc1
- llvmorg-13.0.0
- llvmorg-13.0.0-rc4
- llvmorg-13.0.0-rc3
- llvmorg-13.0.0-rc2
- llvmorg-13.0.0-rc1
- llvmorg-13-init
- llvmorg-12.0.1
- llvmorg-12.0.1-rc4
- llvmorg-12.0.1-rc3
- llvmorg-12.0.1-rc2
- llvmorg-12.0.1-rc1
- llvmorg-12.0.0
- llvmorg-12.0.0-rc5
- llvmorg-12.0.0-rc4
- llvmorg-12.0.0-rc3
- llvmorg-12.0.0-rc2
- llvmorg-12.0.0-rc1
- llvmorg-12-init
- llvmorg-11.1.0
- llvmorg-11.1.0-rc3
- llvmorg-11.1.0-rc2
- llvmorg-11.1.0-rc1
- llvmorg-11.0.1
- llvmorg-11.0.1-rc2
- llvmorg-11.0.1-rc1
- llvmorg-11.0.0
- llvmorg-11.0.0-rc6
- llvmorg-11.0.0-rc5
- llvmorg-11.0.0-rc4
- llvmorg-11.0.0-rc3
- llvmorg-11.0.0-rc2
- llvmorg-11.0.0-rc1
- llvmorg-11-init
- llvmorg-10.0.1
- llvmorg-10.0.1-rc4
- llvmorg-10.0.1-rc3
- llvmorg-10.0.1-rc2
- llvmorg-10.0.1-rc1
- llvmorg-10.0.0
- llvmorg-10.0.0-rc6
- llvmorg-10.0.0-rc5
- llvmorg-10.0.0-rc4
- llvmorg-10.0.0-rc3
- llvmorg-10.0.0-rc2
- llvmorg-10.0.0-rc1
1 parent
df4b9a3
commit 1ff9553
Showing
2 changed files
with
211 additions
and
7 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,185 @@ | ||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py | ||
# RUN: llc -o - %s -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s | ||
--- | ||
name: func0 | ||
tracksRegLiveness: true | ||
stack: | ||
- { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 4, | ||
stack-id: default, callee-saved-register: '', callee-saved-restored: true, | ||
local-offset: -16, debug-info-variable: '', debug-info-expression: '', | ||
debug-info-location: '' } | ||
body: | | ||
bb.0: | ||
; CHECK-LABEL: name: func0 | ||
; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr | ||
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr | ||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 | ||
; CHECK: $sp = frame-setup tSUBspi $sp, 5, 14, $noreg | ||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 56 | ||
; CHECK: $r0 = IMPLICIT_DEF | ||
; CHECK: $r1 = IMPLICIT_DEF | ||
; CHECK: $r2 = IMPLICIT_DEF | ||
; CHECK: $r3 = IMPLICIT_DEF | ||
; CHECK: $r4 = IMPLICIT_DEF | ||
; CHECK: $r5 = IMPLICIT_DEF | ||
; CHECK: $r6 = IMPLICIT_DEF | ||
; CHECK: $r7 = IMPLICIT_DEF | ||
; CHECK: $r8 = IMPLICIT_DEF | ||
; CHECK: $r9 = IMPLICIT_DEF | ||
; CHECK: $r10 = IMPLICIT_DEF | ||
; CHECK: $r11 = IMPLICIT_DEF | ||
; CHECK: $r12 = IMPLICIT_DEF | ||
; CHECK: $lr = IMPLICIT_DEF | ||
; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.1) | ||
; CHECK: $r0 = tMOVr killed $sp, 14, $noreg | ||
; CHECK: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg :: (load 4 from %stack.0 + 12) | ||
; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.1) | ||
; CHECK: KILL $r0 | ||
; CHECK: KILL $r1 | ||
; CHECK: KILL $r2 | ||
; CHECK: KILL $r3 | ||
; CHECK: KILL $r4 | ||
; CHECK: KILL $r5 | ||
; CHECK: KILL $r6 | ||
; CHECK: KILL $r7 | ||
; CHECK: KILL $r8 | ||
; CHECK: KILL $r9 | ||
; CHECK: KILL $r10 | ||
; CHECK: KILL $r11 | ||
; CHECK: KILL $r12 | ||
; CHECK: KILL $lr | ||
$r0 = IMPLICIT_DEF | ||
$r1 = IMPLICIT_DEF | ||
$r2 = IMPLICIT_DEF | ||
$r3 = IMPLICIT_DEF | ||
$r4 = IMPLICIT_DEF | ||
$r5 = IMPLICIT_DEF | ||
$r6 = IMPLICIT_DEF | ||
$r7 = IMPLICIT_DEF | ||
$r8 = IMPLICIT_DEF | ||
$r9 = IMPLICIT_DEF | ||
$r10 = IMPLICIT_DEF | ||
$r11 = IMPLICIT_DEF | ||
$r12 = IMPLICIT_DEF | ||
$lr = IMPLICIT_DEF | ||
renamable $q2 = MVE_VLDRBU32 %stack.0, 12, 0, $noreg :: (load 4 from %stack.0 + 12) | ||
KILL $r0 | ||
KILL $r1 | ||
KILL $r2 | ||
KILL $r3 | ||
KILL $r4 | ||
KILL $r5 | ||
KILL $r6 | ||
KILL $r7 | ||
KILL $r8 | ||
KILL $r9 | ||
KILL $r10 | ||
KILL $r11 | ||
KILL $r12 | ||
KILL $lr | ||
... | ||
--- | ||
name: func1 | ||
tracksRegLiveness: true | ||
stack: | ||
- { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 4, | ||
stack-id: default, callee-saved-register: '', callee-saved-restored: true, | ||
local-offset: -1200, debug-info-variable: '', debug-info-expression: '', | ||
debug-info-location: '' } | ||
- { id: 1, name: '', type: default, offset: 0, size: 1200, alignment: 4, | ||
stack-id: default, callee-saved-register: '', callee-saved-restored: true, | ||
local-offset: -1200, debug-info-variable: '', debug-info-expression: '', | ||
debug-info-location: '' } | ||
body: | | ||
bb.0: | ||
; CHECK-LABEL: name: func1 | ||
; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr | ||
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr | ||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 | ||
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 | ||
; CHECK: $sp = frame-setup t2SUBri killed $sp, 1216, 14, $noreg, $noreg | ||
; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg | ||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1256 | ||
; CHECK: $r0 = IMPLICIT_DEF | ||
; CHECK: $r1 = IMPLICIT_DEF | ||
; CHECK: $r2 = IMPLICIT_DEF | ||
; CHECK: $r3 = IMPLICIT_DEF | ||
; CHECK: $r4 = IMPLICIT_DEF | ||
; CHECK: $r5 = IMPLICIT_DEF | ||
; CHECK: $r6 = IMPLICIT_DEF | ||
; CHECK: $r7 = IMPLICIT_DEF | ||
; CHECK: $r8 = IMPLICIT_DEF | ||
; CHECK: $r9 = IMPLICIT_DEF | ||
; CHECK: $r10 = IMPLICIT_DEF | ||
; CHECK: $r11 = IMPLICIT_DEF | ||
; CHECK: $r12 = IMPLICIT_DEF | ||
; CHECK: $lr = IMPLICIT_DEF | ||
; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.2) | ||
; CHECK: $r0 = t2ADDri killed $sp, 1152, 14, $noreg, $noreg | ||
; CHECK: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg :: (load 4 from %stack.0) | ||
; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.2) | ||
; CHECK: KILL $r0 | ||
; CHECK: KILL $r1 | ||
; CHECK: KILL $r2 | ||
; CHECK: KILL $r3 | ||
; CHECK: KILL $r4 | ||
; CHECK: KILL $r5 | ||
; CHECK: KILL $r6 | ||
; CHECK: KILL $r7 | ||
; CHECK: KILL $r8 | ||
; CHECK: KILL $r9 | ||
; CHECK: KILL $r10 | ||
; CHECK: KILL $r11 | ||
; CHECK: KILL $r12 | ||
; CHECK: KILL $lr | ||
$r0 = IMPLICIT_DEF | ||
$r1 = IMPLICIT_DEF | ||
$r2 = IMPLICIT_DEF | ||
$r3 = IMPLICIT_DEF | ||
$r4 = IMPLICIT_DEF | ||
$r5 = IMPLICIT_DEF | ||
$r6 = IMPLICIT_DEF | ||
$r7 = IMPLICIT_DEF | ||
$r8 = IMPLICIT_DEF | ||
$r9 = IMPLICIT_DEF | ||
$r10 = IMPLICIT_DEF | ||
$r11 = IMPLICIT_DEF | ||
$r12 = IMPLICIT_DEF | ||
$lr = IMPLICIT_DEF | ||
renamable $q2 = MVE_VLDRBU8 %stack.0, 0, 0, $noreg :: (load 4 from %stack.0) | ||
KILL $r0 | ||
KILL $r1 | ||
KILL $r2 | ||
KILL $r3 | ||
KILL $r4 | ||
KILL $r5 | ||
KILL $r6 | ||
KILL $r7 | ||
KILL $r8 | ||
KILL $r9 | ||
KILL $r10 | ||
KILL $r11 | ||
KILL $r12 | ||
KILL $lr | ||
... |