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[GlobalISel] Make the InstructionSelector instance non-const, allowin…
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…g state to be maintained.

Currently we can't keep any state in the selector object that we get from
subtarget. As a result we have to plumb through all our variables through
multiple functions. This change makes it non-const and adds a virtual init()
method to allow further state to be captured for each target.

AArch64 makes use of this in this patch to cache a call to hasFnAttribute()
which is expensive to call, and is used on each selection of G_BRCOND.

Differential Revision: https://reviews.llvm.org/D65984

llvm-svn: 368652
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aemerson committed Aug 13, 2019
1 parent ab04ad6 commit e14c91b
Showing 18 changed files with 76 additions and 68 deletions.
11 changes: 10 additions & 1 deletion llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
Original file line number Diff line number Diff line change
@@ -372,7 +372,16 @@ class InstructionSelector {
/// if returns true:
/// for I in all mutated/inserted instructions:
/// !isPreISelGenericOpcode(I.getOpcode())
virtual bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const = 0;
virtual bool select(MachineInstr &I) = 0;

CodeGenCoverage *CoverageInfo = nullptr;
MachineFunction *MF = nullptr;

/// Setup per-MF selector state.
virtual void setupMF(MachineFunction &mf, CodeGenCoverage &covinfo) {
CoverageInfo = &covinfo;
MF = &mf;
}

protected:
using ComplexRendererFns =
2 changes: 1 addition & 1 deletion llvm/include/llvm/CodeGen/TargetSubtargetInfo.h
Original file line number Diff line number Diff line change
@@ -106,7 +106,7 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
// us do things like a dedicated avx512 selector). However, we might want
// to also specialize selectors by MachineFunction, which would let us be
// aware of optsize/optnone and such.
virtual const InstructionSelector *getInstructionSelector() const {
virtual InstructionSelector *getInstructionSelector() const {
return nullptr;
}

5 changes: 3 additions & 2 deletions llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
Original file line number Diff line number Diff line change
@@ -66,9 +66,10 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');

const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
const InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
CodeGenCoverage CoverageInfo;
assert(ISel && "Cannot work without InstructionSelector");
ISel->setupMF(MF, CoverageInfo);

// An optimization remark emitter. Used to report failures.
MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
@@ -124,7 +125,7 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
continue;
}

if (!ISel->select(MI, CoverageInfo)) {
if (!ISel->select(MI)) {
// FIXME: It would be nice to dump all inserted instructions. It's
// not obvious how, esp. considering select() can insert after MI.
reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select", MI);
18 changes: 14 additions & 4 deletions llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
Original file line number Diff line number Diff line change
@@ -51,9 +51,18 @@ class AArch64InstructionSelector : public InstructionSelector {
const AArch64Subtarget &STI,
const AArch64RegisterBankInfo &RBI);

bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
bool select(MachineInstr &I) override;
static const char *getName() { return DEBUG_TYPE; }

void setupMF(MachineFunction &MF, CodeGenCoverage &CoverageInfo) override {
InstructionSelector::setupMF(MF, CoverageInfo);

// hasFnAttribute() is expensive to call on every BRCOND selection, so
// cache it here for each run of the selector.
ProduceNonFlagSettingCondBr =
!MF.getFunction().hasFnAttribute(Attribute::SpeculativeLoadHardening);
}

private:
/// tblgen-erated 'select' implementation, used as the initial selector for
/// the patterns that don't require complex C++.
@@ -222,6 +231,8 @@ class AArch64InstructionSelector : public InstructionSelector {
const AArch64RegisterInfo &TRI;
const AArch64RegisterBankInfo &RBI;

bool ProduceNonFlagSettingCondBr = false;

#define GET_GLOBALISEL_PREDICATES_DECL
#include "AArch64GenGlobalISel.inc"
#undef GET_GLOBALISEL_PREDICATES_DECL
@@ -1315,8 +1326,7 @@ bool AArch64InstructionSelector::earlySelect(MachineInstr &I) const {
}
}

bool AArch64InstructionSelector::select(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const {
bool AArch64InstructionSelector::select(MachineInstr &I) {
assert(I.getParent() && "Instruction should be in a basic block!");
assert(I.getParent()->getParent() && "Instruction should be in a function!");

@@ -1385,7 +1395,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
if (earlySelect(I))
return true;

if (selectImpl(I, CoverageInfo))
if (selectImpl(I, *CoverageInfo))
return true;

LLT Ty =
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64Subtarget.cpp
Original file line number Diff line number Diff line change
@@ -196,7 +196,7 @@ const CallLowering *AArch64Subtarget::getCallLowering() const {
return CallLoweringInfo.get();
}

const InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
InstructionSelector *AArch64Subtarget::getInstructionSelector() const {
return InstSelector.get();
}

2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64Subtarget.h
Original file line number Diff line number Diff line change
@@ -256,7 +256,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
return &getInstrInfo()->getRegisterInfo();
}
const CallLowering *getCallLowering() const override;
const InstructionSelector *getInstructionSelector() const override;
InstructionSelector *getInstructionSelector() const override;
const LegalizerInfo *getLegalizerInfo() const override;
const RegisterBankInfo *getRegBankInfo() const override;
const Triple &getTargetTriple() const { return TargetTriple; }
36 changes: 16 additions & 20 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
Original file line number Diff line number Diff line change
@@ -563,8 +563,7 @@ bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const {
return true;
}

bool AMDGPUInstructionSelector::selectG_INTRINSIC(
MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
unsigned IntrinsicID = I.getOperand(I.getNumExplicitDefs()).getIntrinsicID();
switch (IntrinsicID) {
case Intrinsic::amdgcn_if_break: {
@@ -593,7 +592,7 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC(
return true;
}
default:
return selectImpl(I, CoverageInfo);
return selectImpl(I, *CoverageInfo);
}
}

@@ -733,7 +732,7 @@ buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt,
}

bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
MachineInstr &I) const {
MachineBasicBlock *BB = I.getParent();
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
@@ -787,7 +786,7 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
return true;
}
default:
return selectImpl(I, CoverageInfo);
return selectImpl(I, *CoverageInfo);
}
}

@@ -840,10 +839,9 @@ bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
return Ret;
}

bool AMDGPUInstructionSelector::selectG_STORE(
MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const {
initM0(I);
return selectImpl(I, CoverageInfo);
return selectImpl(I, *CoverageInfo);
}

static int sizeToSubRegIndex(unsigned Size) {
@@ -1215,10 +1213,9 @@ void AMDGPUInstructionSelector::initM0(MachineInstr &I) const {
}
}

bool AMDGPUInstructionSelector::selectG_LOAD_ATOMICRMW(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const {
bool AMDGPUInstructionSelector::selectG_LOAD_ATOMICRMW(MachineInstr &I) const {
initM0(I);
return selectImpl(I, CoverageInfo);
return selectImpl(I, *CoverageInfo);
}

bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
@@ -1282,8 +1279,7 @@ bool AMDGPUInstructionSelector::selectG_FRAME_INDEX(MachineInstr &I) const {
DstReg, IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass, MRI);
}

bool AMDGPUInstructionSelector::select(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const {
bool AMDGPUInstructionSelector::select(MachineInstr &I) {
if (I.isPHI())
return selectPHI(I);

@@ -1299,14 +1295,14 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
case TargetOpcode::G_XOR:
if (selectG_AND_OR_XOR(I))
return true;
return selectImpl(I, CoverageInfo);
return selectImpl(I, *CoverageInfo);
case TargetOpcode::G_ADD:
case TargetOpcode::G_SUB:
if (selectG_ADD_SUB(I))
return true;
LLVM_FALLTHROUGH;
default:
return selectImpl(I, CoverageInfo);
return selectImpl(I, *CoverageInfo);
case TargetOpcode::G_INTTOPTR:
case TargetOpcode::G_BITCAST:
return selectCOPY(I);
@@ -1328,13 +1324,13 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
case TargetOpcode::G_INSERT:
return selectG_INSERT(I);
case TargetOpcode::G_INTRINSIC:
return selectG_INTRINSIC(I, CoverageInfo);
return selectG_INTRINSIC(I);
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
return selectG_INTRINSIC_W_SIDE_EFFECTS(I, CoverageInfo);
return selectG_INTRINSIC_W_SIDE_EFFECTS(I);
case TargetOpcode::G_ICMP:
if (selectG_ICMP(I))
return true;
return selectImpl(I, CoverageInfo);
return selectImpl(I, *CoverageInfo);
case TargetOpcode::G_LOAD:
case TargetOpcode::G_ATOMIC_CMPXCHG:
case TargetOpcode::G_ATOMICRMW_XCHG:
@@ -1348,11 +1344,11 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
case TargetOpcode::G_ATOMICRMW_UMIN:
case TargetOpcode::G_ATOMICRMW_UMAX:
case TargetOpcode::G_ATOMICRMW_FADD:
return selectG_LOAD_ATOMICRMW(I, CoverageInfo);
return selectG_LOAD_ATOMICRMW(I);
case TargetOpcode::G_SELECT:
return selectG_SELECT(I);
case TargetOpcode::G_STORE:
return selectG_STORE(I, CoverageInfo);
return selectG_STORE(I);
case TargetOpcode::G_TRUNC:
return selectG_TRUNC(I);
case TargetOpcode::G_SEXT:
11 changes: 5 additions & 6 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
Original file line number Diff line number Diff line change
@@ -47,7 +47,7 @@ class AMDGPUInstructionSelector : public InstructionSelector {
const AMDGPURegisterBankInfo &RBI,
const AMDGPUTargetMachine &TM);

bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
bool select(MachineInstr &I) override;
static const char *getName();

private:
@@ -81,9 +81,8 @@ class AMDGPUInstructionSelector : public InstructionSelector {
bool selectG_GEP(MachineInstr &I) const;
bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
bool selectG_INSERT(MachineInstr &I) const;
bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const;
bool selectG_INTRINSIC(MachineInstr &I) const;
bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
bool selectG_ICMP(MachineInstr &I) const;
bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
@@ -92,8 +91,8 @@ class AMDGPUInstructionSelector : public InstructionSelector {
bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;

void initM0(MachineInstr &I) const;
bool selectG_LOAD_ATOMICRMW(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
bool selectG_STORE(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
bool selectG_LOAD_ATOMICRMW(MachineInstr &I) const;
bool selectG_STORE(MachineInstr &I) const;
bool selectG_SELECT(MachineInstr &I) const;
bool selectG_BRCOND(MachineInstr &I) const;
bool selectG_FRAME_INDEX(MachineInstr &I) const;
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
Original file line number Diff line number Diff line change
@@ -422,7 +422,7 @@ class GCNSubtarget : public AMDGPUGenSubtargetInfo,
return CallLoweringInfo.get();
}

const InstructionSelector *getInstructionSelector() const override {
InstructionSelector *getInstructionSelector() const override {
return InstSelector.get();
}

7 changes: 3 additions & 4 deletions llvm/lib/Target/ARM/ARMInstructionSelector.cpp
Original file line number Diff line number Diff line change
@@ -34,7 +34,7 @@ class ARMInstructionSelector : public InstructionSelector {
ARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
const ARMRegisterBankInfo &RBI);

bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
bool select(MachineInstr &I) override;
static const char *getName() { return DEBUG_TYPE; }

private:
@@ -833,8 +833,7 @@ void ARMInstructionSelector::renderVFPF64Imm(
NewInstBuilder.addImm(FPImmEncoding);
}

bool ARMInstructionSelector::select(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const {
bool ARMInstructionSelector::select(MachineInstr &I) {
assert(I.getParent() && "Instruction should be in a basic block!");
assert(I.getParent()->getParent() && "Instruction should be in a function!");

@@ -851,7 +850,7 @@ bool ARMInstructionSelector::select(MachineInstr &I,

using namespace TargetOpcode;

if (selectImpl(I, CoverageInfo))
if (selectImpl(I, *CoverageInfo))
return true;

MachineInstrBuilder MIB{MF, I};
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMSubtarget.cpp
Original file line number Diff line number Diff line change
@@ -125,7 +125,7 @@ const CallLowering *ARMSubtarget::getCallLowering() const {
return CallLoweringInfo.get();
}

const InstructionSelector *ARMSubtarget::getInstructionSelector() const {
InstructionSelector *ARMSubtarget::getInstructionSelector() const {
return InstSelector.get();
}

2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMSubtarget.h
Original file line number Diff line number Diff line change
@@ -536,7 +536,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
}

const CallLowering *getCallLowering() const override;
const InstructionSelector *getInstructionSelector() const override;
InstructionSelector *getInstructionSelector() const override;
const LegalizerInfo *getLegalizerInfo() const override;
const RegisterBankInfo *getRegBankInfo() const override;

7 changes: 3 additions & 4 deletions llvm/lib/Target/Mips/MipsInstructionSelector.cpp
Original file line number Diff line number Diff line change
@@ -34,7 +34,7 @@ class MipsInstructionSelector : public InstructionSelector {
MipsInstructionSelector(const MipsTargetMachine &TM, const MipsSubtarget &STI,
const MipsRegisterBankInfo &RBI);

bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
bool select(MachineInstr &I) override;
static const char *getName() { return DEBUG_TYPE; }

private:
@@ -204,8 +204,7 @@ static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned MemSizeInBytes,
return Opc;
}

bool MipsInstructionSelector::select(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const {
bool MipsInstructionSelector::select(MachineInstr &I) {

MachineBasicBlock &MBB = *I.getParent();
MachineFunction &MF = *MBB.getParent();
@@ -232,7 +231,7 @@ bool MipsInstructionSelector::select(MachineInstr &I,
return true;
}

if (selectImpl(I, CoverageInfo))
if (selectImpl(I, *CoverageInfo))
return true;

MachineInstr *MI = nullptr;
2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsSubtarget.cpp
Original file line number Diff line number Diff line change
@@ -286,6 +286,6 @@ const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const {
return RegBankInfo.get();
}

const InstructionSelector *MipsSubtarget::getInstructionSelector() const {
InstructionSelector *MipsSubtarget::getInstructionSelector() const {
return InstSelector.get();
}
2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsSubtarget.h
Original file line number Diff line number Diff line change
@@ -391,7 +391,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
const CallLowering *getCallLowering() const override;
const LegalizerInfo *getLegalizerInfo() const override;
const RegisterBankInfo *getRegBankInfo() const override;
const InstructionSelector *getInstructionSelector() const override;
InstructionSelector *getInstructionSelector() const override;
};
} // End llvm namespace

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