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LebedevRILebedevRI
committedJul 30, 2019
[DivRemPairs] Add srem-of-srem tests (PR42823, D65298, D65451)
The @srem_of_srem_expanded case exposed a RAUW pitfall in D65298. Right now these don't appear to fail verification, so it should be safe to precommit them. https://reviews.llvm.org/D65298 https://bugs.llvm.org/show_bug.cgi?id=42823 https://reviews.llvm.org/D65451 llvm-svn: 367325
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‎llvm/test/Transforms/DivRemPairs/PowerPC/div-expanded-rem-pair.ll

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Original file line numberDiff line numberDiff line change
@@ -95,6 +95,51 @@ end:
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ret i8 %ret
9696
}
9797

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; Be careful with RAUW/invalidation if this is a srem-of-srem.
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define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_unexpanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[T1]], [[T0]]
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; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[X]], [[TMP1]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[TMP2]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: ret i32 [[TMP4]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3.recomposed = srem i32 %X, %t0
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%t4 = sdiv i32 %t3.recomposed, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6.recomposed = srem i32 %t3.recomposed, %Y
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ret i32 %t6.recomposed
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}
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define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_expanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]]
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; CHECK-NEXT: ret i32 [[T6]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3 = sub nsw i32 %X, %t2
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%t4 = sdiv i32 %t3, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6 = sub nsw i32 %t3, %t5
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ret i32 %t6
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}
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98143
; If the target doesn't have a unified div/rem op for the type, keep decomposed rem
99144

100145
define i128 @dont_hoist_urem(i128 %a, i128 %b) {

‎llvm/test/Transforms/DivRemPairs/PowerPC/div-rem-pairs.ll

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Original file line numberDiff line numberDiff line change
@@ -151,6 +151,51 @@ end:
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ret i8 %ret
152152
}
153153

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; Be careful with RAUW/invalidation if this is a srem-of-srem.
155+
156+
define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_unexpanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[T1]], [[T0]]
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; CHECK-NEXT: [[TMP2:%.*]] = sub i32 [[X]], [[TMP1]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[TMP2]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[TMP4:%.*]] = sub i32 [[TMP2]], [[TMP3]]
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; CHECK-NEXT: ret i32 [[TMP4]]
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;
169+
%t0 = mul nsw i32 %Z, %Y
170+
%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3.recomposed = srem i32 %X, %t0
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%t4 = sdiv i32 %t3.recomposed, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6.recomposed = srem i32 %t3.recomposed, %Y
176+
ret i32 %t6.recomposed
177+
}
178+
define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
179+
; CHECK-LABEL: @srem_of_srem_expanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]]
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; CHECK-NEXT: ret i32 [[T6]]
188+
;
189+
%t0 = mul nsw i32 %Z, %Y
190+
%t1 = sdiv i32 %X, %t0
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%t2 = mul nsw i32 %t0, %t1
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%t3 = sub nsw i32 %X, %t2
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%t4 = sdiv i32 %t3, %Y
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%t5 = mul nsw i32 %t4, %Y
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%t6 = sub nsw i32 %t3, %t5
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ret i32 %t6
197+
}
198+
154199
; If the ops don't match, don't do anything: signedness.
155200

156201
define i32 @dont_hoist_udiv(i32 %a, i32 %b) {

‎llvm/test/Transforms/DivRemPairs/X86/div-expanded-rem-pair.ll

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Original file line numberDiff line numberDiff line change
@@ -95,6 +95,49 @@ end:
9595
ret i8 %ret
9696
}
9797

98+
; Be careful with RAUW/invalidation if this is a srem-of-srem.
99+
100+
define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
101+
; CHECK-LABEL: @srem_of_srem_unexpanded(
102+
; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3_RECOMPOSED:%.*]] = srem i32 [[X]], [[T0]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6_RECOMPOSED:%.*]] = srem i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: ret i32 [[T6_RECOMPOSED]]
110+
;
111+
%t0 = mul nsw i32 %Z, %Y
112+
%t1 = sdiv i32 %X, %t0
113+
%t2 = mul nsw i32 %t0, %t1
114+
%t3.recomposed = srem i32 %X, %t0
115+
%t4 = sdiv i32 %t3.recomposed, %Y
116+
%t5 = mul nsw i32 %t4, %Y
117+
%t6.recomposed = srem i32 %t3.recomposed, %Y
118+
ret i32 %t6.recomposed
119+
}
120+
define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
121+
; CHECK-LABEL: @srem_of_srem_expanded(
122+
; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
124+
; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]]
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; CHECK-NEXT: ret i32 [[T6]]
130+
;
131+
%t0 = mul nsw i32 %Z, %Y
132+
%t1 = sdiv i32 %X, %t0
133+
%t2 = mul nsw i32 %t0, %t1
134+
%t3 = sub nsw i32 %X, %t2
135+
%t4 = sdiv i32 %t3, %Y
136+
%t5 = mul nsw i32 %t4, %Y
137+
%t6 = sub nsw i32 %t3, %t5
138+
ret i32 %t6
139+
}
140+
98141
; If the target doesn't have a unified div/rem op for the type, keep decomposed rem
99142

100143
define i128 @dont_hoist_urem(i128 %a, i128 %b) {

‎llvm/test/Transforms/DivRemPairs/X86/div-rem-pairs.ll

+43
Original file line numberDiff line numberDiff line change
@@ -145,6 +145,49 @@ end:
145145
ret i8 %ret
146146
}
147147

148+
; Be careful with RAUW/invalidation if this is a srem-of-srem.
149+
150+
define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
151+
; CHECK-LABEL: @srem_of_srem_unexpanded(
152+
; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
153+
; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
154+
; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
155+
; CHECK-NEXT: [[T3_RECOMPOSED:%.*]] = srem i32 [[X]], [[T0]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6_RECOMPOSED:%.*]] = srem i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: ret i32 [[T6_RECOMPOSED]]
160+
;
161+
%t0 = mul nsw i32 %Z, %Y
162+
%t1 = sdiv i32 %X, %t0
163+
%t2 = mul nsw i32 %t0, %t1
164+
%t3.recomposed = srem i32 %X, %t0
165+
%t4 = sdiv i32 %t3.recomposed, %Y
166+
%t5 = mul nsw i32 %t4, %Y
167+
%t6.recomposed = srem i32 %t3.recomposed, %Y
168+
ret i32 %t6.recomposed
169+
}
170+
define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
171+
; CHECK-LABEL: @srem_of_srem_expanded(
172+
; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
173+
; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
174+
; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
175+
; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]]
176+
; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
177+
; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
178+
; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]]
179+
; CHECK-NEXT: ret i32 [[T6]]
180+
;
181+
%t0 = mul nsw i32 %Z, %Y
182+
%t1 = sdiv i32 %X, %t0
183+
%t2 = mul nsw i32 %t0, %t1
184+
%t3 = sub nsw i32 %X, %t2
185+
%t4 = sdiv i32 %t3, %Y
186+
%t5 = mul nsw i32 %t4, %Y
187+
%t6 = sub nsw i32 %t3, %t5
188+
ret i32 %t6
189+
}
190+
148191
; If the ops don't match, don't do anything: signedness.
149192

150193
define i32 @dont_hoist_udiv(i32 %a, i32 %b) {

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