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statham-armstatham-arm
committedJun 21, 2019
[ARM] Add a batch of similarly encoded MVE instructions.
Summary: This adds the `MVE_qDest_qSrc` superclass and all instructions that inherit from it. It's not the complete class of _everything_ with a q-register as both destination and source; it's a subset of them that all have similar encodings (but it would have been hopelessly unwieldy to call it anything like MVE_111x11100). This category includes add/sub with carry; long multiplies; halving multiplies; multiply and accumulate, and some more complex instructions. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62677 llvm-svn: 364037
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‎llvm/lib/Target/ARM/ARMInstrMVE.td

Lines changed: 278 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2404,6 +2404,284 @@ def MVE_VCMPs32r : MVE_VCMPqrs<"s32", 0b10>;
24042404

24052405
// end of MVE compares
24062406

2407+
// start of MVE_qDest_qSrc
2408+
2409+
class MVE_qDest_qSrc<string iname, string suffix, dag oops, dag iops,
2410+
string ops, vpred_ops vpred, string cstr,
2411+
list<dag> pattern=[]>
2412+
: MVE_p<oops, iops, NoItinerary, iname, suffix,
2413+
ops, vpred, cstr, pattern> {
2414+
bits<4> Qd;
2415+
bits<4> Qm;
2416+
2417+
let Inst{25-23} = 0b100;
2418+
let Inst{22} = Qd{3};
2419+
let Inst{15-13} = Qd{2-0};
2420+
let Inst{11-9} = 0b111;
2421+
let Inst{6} = 0b0;
2422+
let Inst{5} = Qm{3};
2423+
let Inst{4} = 0b0;
2424+
let Inst{3-1} = Qm{2-0};
2425+
}
2426+
2427+
class MVE_VQxDMLxDH<string iname, bit exch, bit round, bit subtract,
2428+
string suffix, bits<2> size, list<dag> pattern=[]>
2429+
: MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
2430+
(ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
2431+
vpred_r, "", pattern> {
2432+
bits<4> Qn;
2433+
2434+
let Inst{28} = subtract;
2435+
let Inst{21-20} = size;
2436+
let Inst{19-17} = Qn{2-0};
2437+
let Inst{16} = 0b0;
2438+
let Inst{12} = exch;
2439+
let Inst{8} = 0b0;
2440+
let Inst{7} = Qn{3};
2441+
let Inst{0} = round;
2442+
}
2443+
2444+
multiclass MVE_VQxDMLxDH_multi<string iname, bit exch,
2445+
bit round, bit subtract> {
2446+
def s8 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s8", 0b00>;
2447+
def s16 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s16", 0b01>;
2448+
def s32 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s32", 0b10>;
2449+
}
2450+
2451+
defm MVE_VQDMLADH : MVE_VQxDMLxDH_multi<"vqdmladh", 0b0, 0b0, 0b0>;
2452+
defm MVE_VQDMLADHX : MVE_VQxDMLxDH_multi<"vqdmladhx", 0b1, 0b0, 0b0>;
2453+
defm MVE_VQRDMLADH : MVE_VQxDMLxDH_multi<"vqrdmladh", 0b0, 0b1, 0b0>;
2454+
defm MVE_VQRDMLADHX : MVE_VQxDMLxDH_multi<"vqrdmladhx", 0b1, 0b1, 0b0>;
2455+
defm MVE_VQDMLSDH : MVE_VQxDMLxDH_multi<"vqdmlsdh", 0b0, 0b0, 0b1>;
2456+
defm MVE_VQDMLSDHX : MVE_VQxDMLxDH_multi<"vqdmlsdhx", 0b1, 0b0, 0b1>;
2457+
defm MVE_VQRDMLSDH : MVE_VQxDMLxDH_multi<"vqrdmlsdh", 0b0, 0b1, 0b1>;
2458+
defm MVE_VQRDMLSDHX : MVE_VQxDMLxDH_multi<"vqrdmlsdhx", 0b1, 0b1, 0b1>;
2459+
2460+
class MVE_VCMUL<string iname, string suffix, bit size, list<dag> pattern=[]>
2461+
: MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
2462+
(ins MQPR:$Qn, MQPR:$Qm, complexrotateop:$rot),
2463+
"$Qd, $Qn, $Qm, $rot", vpred_r, "", pattern> {
2464+
bits<4> Qn;
2465+
bits<2> rot;
2466+
2467+
let Inst{28} = size;
2468+
let Inst{21-20} = 0b11;
2469+
let Inst{19-17} = Qn{2-0};
2470+
let Inst{16} = 0b0;
2471+
let Inst{12} = rot{1};
2472+
let Inst{8} = 0b0;
2473+
let Inst{7} = Qn{3};
2474+
let Inst{0} = rot{0};
2475+
2476+
let Predicates = [HasMVEFloat];
2477+
}
2478+
2479+
def MVE_VCMULf16 : MVE_VCMUL<"vcmul", "f16", 0b0>;
2480+
def MVE_VCMULf32 : MVE_VCMUL<"vcmul", "f32", 0b1>;
2481+
2482+
class MVE_VMULL<string iname, string suffix, bit bit_28, bits<2> bits_21_20,
2483+
bit T, list<dag> pattern=[]>
2484+
: MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
2485+
(ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
2486+
vpred_r, "", pattern> {
2487+
bits<4> Qd;
2488+
bits<4> Qn;
2489+
bits<4> Qm;
2490+
2491+
let Inst{28} = bit_28;
2492+
let Inst{21-20} = bits_21_20;
2493+
let Inst{19-17} = Qn{2-0};
2494+
let Inst{16} = 0b1;
2495+
let Inst{12} = T;
2496+
let Inst{8} = 0b0;
2497+
let Inst{7} = Qn{3};
2498+
let Inst{0} = 0b0;
2499+
}
2500+
2501+
multiclass MVE_VMULL_multi<string iname, string suffix,
2502+
bit bit_28, bits<2> bits_21_20> {
2503+
def bh : MVE_VMULL<iname # "b", suffix, bit_28, bits_21_20, 0b0>;
2504+
def th : MVE_VMULL<iname # "t", suffix, bit_28, bits_21_20, 0b1>;
2505+
}
2506+
2507+
// For integer multiplies, bits 21:20 encode size, and bit 28 signedness.
2508+
// For polynomial multiplies, bits 21:20 take the unused value 0b11, and
2509+
// bit 28 switches to encoding the size.
2510+
2511+
defm MVE_VMULLs8 : MVE_VMULL_multi<"vmull", "s8", 0b0, 0b00>;
2512+
defm MVE_VMULLs16 : MVE_VMULL_multi<"vmull", "s16", 0b0, 0b01>;
2513+
defm MVE_VMULLs32 : MVE_VMULL_multi<"vmull", "s32", 0b0, 0b10>;
2514+
defm MVE_VMULLu8 : MVE_VMULL_multi<"vmull", "u8", 0b1, 0b00>;
2515+
defm MVE_VMULLu16 : MVE_VMULL_multi<"vmull", "u16", 0b1, 0b01>;
2516+
defm MVE_VMULLu32 : MVE_VMULL_multi<"vmull", "u32", 0b1, 0b10>;
2517+
defm MVE_VMULLp8 : MVE_VMULL_multi<"vmull", "p8", 0b0, 0b11>;
2518+
defm MVE_VMULLp16 : MVE_VMULL_multi<"vmull", "p16", 0b1, 0b11>;
2519+
2520+
class MVE_VxMULH<string iname, string suffix, bit U, bits<2> size,
2521+
bit round, list<dag> pattern=[]>
2522+
: MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
2523+
(ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
2524+
vpred_r, "", pattern> {
2525+
bits<4> Qn;
2526+
2527+
let Inst{28} = U;
2528+
let Inst{21-20} = size;
2529+
let Inst{19-17} = Qn{2-0};
2530+
let Inst{16} = 0b1;
2531+
let Inst{12} = round;
2532+
let Inst{8} = 0b0;
2533+
let Inst{7} = Qn{3};
2534+
let Inst{0} = 0b1;
2535+
}
2536+
2537+
def MVE_VMULHs8 : MVE_VxMULH<"vmulh", "s8", 0b0, 0b00, 0b0>;
2538+
def MVE_VMULHs16 : MVE_VxMULH<"vmulh", "s16", 0b0, 0b01, 0b0>;
2539+
def MVE_VMULHs32 : MVE_VxMULH<"vmulh", "s32", 0b0, 0b10, 0b0>;
2540+
def MVE_VMULHu8 : MVE_VxMULH<"vmulh", "u8", 0b1, 0b00, 0b0>;
2541+
def MVE_VMULHu16 : MVE_VxMULH<"vmulh", "u16", 0b1, 0b01, 0b0>;
2542+
def MVE_VMULHu32 : MVE_VxMULH<"vmulh", "u32", 0b1, 0b10, 0b0>;
2543+
2544+
def MVE_VRMULHs8 : MVE_VxMULH<"vrmulh", "s8", 0b0, 0b00, 0b1>;
2545+
def MVE_VRMULHs16 : MVE_VxMULH<"vrmulh", "s16", 0b0, 0b01, 0b1>;
2546+
def MVE_VRMULHs32 : MVE_VxMULH<"vrmulh", "s32", 0b0, 0b10, 0b1>;
2547+
def MVE_VRMULHu8 : MVE_VxMULH<"vrmulh", "u8", 0b1, 0b00, 0b1>;
2548+
def MVE_VRMULHu16 : MVE_VxMULH<"vrmulh", "u16", 0b1, 0b01, 0b1>;
2549+
def MVE_VRMULHu32 : MVE_VxMULH<"vrmulh", "u32", 0b1, 0b10, 0b1>;
2550+
2551+
class MVE_VxMOVxN<string iname, string suffix, bit bit_28, bit bit_17,
2552+
bits<2> size, bit T, list<dag> pattern=[]>
2553+
: MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
2554+
(ins MQPR:$Qd_src, MQPR:$Qm), "$Qd, $Qm",
2555+
vpred_n, "$Qd = $Qd_src", pattern> {
2556+
2557+
let Inst{28} = bit_28;
2558+
let Inst{21-20} = 0b11;
2559+
let Inst{19-18} = size;
2560+
let Inst{17} = bit_17;
2561+
let Inst{16} = 0b1;
2562+
let Inst{12} = T;
2563+
let Inst{8} = 0b0;
2564+
let Inst{7} = !if(!eq(bit_17, 0), 1, 0);
2565+
let Inst{0} = 0b1;
2566+
}
2567+
2568+
multiclass MVE_VxMOVxN_halves<string iname, string suffix,
2569+
bit bit_28, bit bit_17, bits<2> size> {
2570+
def bh : MVE_VxMOVxN<iname # "b", suffix, bit_28, bit_17, size, 0b0>;
2571+
def th : MVE_VxMOVxN<iname # "t", suffix, bit_28, bit_17, size, 0b1>;
2572+
}
2573+
2574+
defm MVE_VMOVNi16 : MVE_VxMOVxN_halves<"vmovn", "i16", 0b1, 0b0, 0b00>;
2575+
defm MVE_VMOVNi32 : MVE_VxMOVxN_halves<"vmovn", "i32", 0b1, 0b0, 0b01>;
2576+
defm MVE_VQMOVNs16 : MVE_VxMOVxN_halves<"vqmovn", "s16", 0b0, 0b1, 0b00>;
2577+
defm MVE_VQMOVNs32 : MVE_VxMOVxN_halves<"vqmovn", "s32", 0b0, 0b1, 0b01>;
2578+
defm MVE_VQMOVNu16 : MVE_VxMOVxN_halves<"vqmovn", "u16", 0b1, 0b1, 0b00>;
2579+
defm MVE_VQMOVNu32 : MVE_VxMOVxN_halves<"vqmovn", "u32", 0b1, 0b1, 0b01>;
2580+
defm MVE_VQMOVUNs16 : MVE_VxMOVxN_halves<"vqmovun", "s16", 0b0, 0b0, 0b00>;
2581+
defm MVE_VQMOVUNs32 : MVE_VxMOVxN_halves<"vqmovun", "s32", 0b0, 0b0, 0b01>;
2582+
2583+
class MVE_VCVT_ff<string iname, string suffix, bit op, bit T,
2584+
list<dag> pattern=[]>
2585+
: MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
2586+
"$Qd, $Qm", vpred_n, "$Qd = $Qd_src", pattern> {
2587+
let Inst{28} = op;
2588+
let Inst{21-16} = 0b111111;
2589+
let Inst{12} = T;
2590+
let Inst{8-7} = 0b00;
2591+
let Inst{0} = 0b1;
2592+
2593+
let Predicates = [HasMVEFloat];
2594+
}
2595+
2596+
multiclass MVE_VCVT_ff_halves<string suffix, bit op> {
2597+
def bh : MVE_VCVT_ff<"vcvtb", suffix, op, 0b0>;
2598+
def th : MVE_VCVT_ff<"vcvtt", suffix, op, 0b1>;
2599+
}
2600+
2601+
defm MVE_VCVTf16f32 : MVE_VCVT_ff_halves<"f16.f32", 0b0>;
2602+
defm MVE_VCVTf32f16 : MVE_VCVT_ff_halves<"f32.f16", 0b1>;
2603+
2604+
class MVE_VxCADD<string iname, string suffix, bits<2> size, bit halve,
2605+
list<dag> pattern=[]>
2606+
: MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
2607+
(ins MQPR:$Qn, MQPR:$Qm, complexrotateopodd:$rot),
2608+
"$Qd, $Qn, $Qm, $rot", vpred_r, "",
2609+
pattern> {
2610+
bits<4> Qn;
2611+
bit rot;
2612+
2613+
let Inst{28} = halve;
2614+
let Inst{21-20} = size;
2615+
let Inst{19-17} = Qn{2-0};
2616+
let Inst{16} = 0b0;
2617+
let Inst{12} = rot;
2618+
let Inst{8} = 0b1;
2619+
let Inst{7} = Qn{3};
2620+
let Inst{0} = 0b0;
2621+
}
2622+
2623+
def MVE_VCADDi8 : MVE_VxCADD<"vcadd", "i8", 0b00, 0b1>;
2624+
def MVE_VCADDi16 : MVE_VxCADD<"vcadd", "i16", 0b01, 0b1>;
2625+
def MVE_VCADDi32 : MVE_VxCADD<"vcadd", "i32", 0b10, 0b1>;
2626+
2627+
def MVE_VHCADDs8 : MVE_VxCADD<"vhcadd", "s8", 0b00, 0b0>;
2628+
def MVE_VHCADDs16 : MVE_VxCADD<"vhcadd", "s16", 0b01, 0b0>;
2629+
def MVE_VHCADDs32 : MVE_VxCADD<"vhcadd", "s32", 0b10, 0b0>;
2630+
2631+
class MVE_VADCSBC<string iname, bit I, bit subtract,
2632+
dag carryin, list<dag> pattern=[]>
2633+
: MVE_qDest_qSrc<iname, "i32", (outs MQPR:$Qd, cl_FPSCR_NZCV:$carryout),
2634+
!con((ins MQPR:$Qn, MQPR:$Qm), carryin),
2635+
"$Qd, $Qn, $Qm", vpred_r, "", pattern> {
2636+
bits<4> Qn;
2637+
2638+
let Inst{28} = subtract;
2639+
let Inst{21-20} = 0b11;
2640+
let Inst{19-17} = Qn{2-0};
2641+
let Inst{16} = 0b0;
2642+
let Inst{12} = I;
2643+
let Inst{8} = 0b1;
2644+
let Inst{7} = Qn{3};
2645+
let Inst{0} = 0b0;
2646+
2647+
// Custom decoder method in order to add the FPSCR operand(s), which
2648+
// Tablegen won't do right
2649+
let DecoderMethod = "DecodeMVEVADCInstruction";
2650+
}
2651+
2652+
def MVE_VADC : MVE_VADCSBC<"vadc", 0b0, 0b0, (ins cl_FPSCR_NZCV:$carryin)>;
2653+
def MVE_VADCI : MVE_VADCSBC<"vadci", 0b1, 0b0, (ins)>;
2654+
2655+
def MVE_VSBC : MVE_VADCSBC<"vsbc", 0b0, 0b1, (ins cl_FPSCR_NZCV:$carryin)>;
2656+
def MVE_VSBCI : MVE_VADCSBC<"vsbci", 0b1, 0b1, (ins)>;
2657+
2658+
class MVE_VQDMULL<string iname, string suffix, bit size, bit T,
2659+
list<dag> pattern=[]>
2660+
: MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
2661+
(ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
2662+
vpred_r, "", pattern> {
2663+
bits<4> Qn;
2664+
2665+
let Inst{28} = size;
2666+
let Inst{21-20} = 0b11;
2667+
let Inst{19-17} = Qn{2-0};
2668+
let Inst{16} = 0b0;
2669+
let Inst{12} = T;
2670+
let Inst{8} = 0b1;
2671+
let Inst{7} = Qn{3};
2672+
let Inst{0} = 0b1;
2673+
}
2674+
2675+
multiclass MVE_VQDMULL_halves<string suffix, bit size> {
2676+
def bh : MVE_VQDMULL<"vqdmullb", suffix, size, 0b0>;
2677+
def th : MVE_VQDMULL<"vqdmullt", suffix, size, 0b1>;
2678+
}
2679+
2680+
defm MVE_VQDMULLs16 : MVE_VQDMULL_halves<"s16", 0b0>;
2681+
defm MVE_VQDMULLs32 : MVE_VQDMULL_halves<"s32", 0b1>;
2682+
2683+
// end of mve_qDest_qSrc
2684+
24072685
class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
24082686
: MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
24092687
bits<3> fc;

‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Lines changed: 40 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5966,6 +5966,7 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
59665966
Mnemonic == "vnege" || Mnemonic == "vnegt" ||
59675967
Mnemonic == "vmule" || Mnemonic == "vmult" ||
59685968
Mnemonic == "vrintne" ||
5969+
Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
59695970
Mnemonic.startswith("vq")))) {
59705971
unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
59715972
if (CC != ~0U) {
@@ -6010,7 +6011,10 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
60106011
if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
60116012
Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
60126013
Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
6013-
Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vcvt") {
6014+
Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
6015+
Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
6016+
Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
6017+
Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
60146018
unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
60156019
if (CC != ~0U) {
60166020
Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
@@ -6683,6 +6687,16 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
66836687
ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc));
66846688
Operands.insert(Operands.begin(),
66856689
ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
6690+
} else if (Mnemonic == "vmul" && PredicationCode == ARMCC::LT &&
6691+
!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
6692+
// Another hack, this time to distinguish between scalar predicated vmul
6693+
// with 'lt' predication code and the vector instruction vmullt with
6694+
// vector predication code "none"
6695+
Operands.erase(Operands.begin() + 1);
6696+
Operands.erase(Operands.begin());
6697+
SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
6698+
Operands.insert(Operands.begin(),
6699+
ARMOperand::CreateToken(StringRef("vmullt"), MLoc));
66866700
}
66876701
// For vmov and vcmp, as mentioned earlier, we did not add the vector
66886702
// predication code, since these may contain operands that require
@@ -7541,6 +7555,31 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
75417555
"list of registers must be at least 1 and at most 16");
75427556
break;
75437557
}
7558+
case ARM::MVE_VQDMULLs32bh:
7559+
case ARM::MVE_VQDMULLs32th:
7560+
case ARM::MVE_VCMULf32:
7561+
case ARM::MVE_VMULLs32bh:
7562+
case ARM::MVE_VMULLs32th:
7563+
case ARM::MVE_VMULLu32bh:
7564+
case ARM::MVE_VMULLu32th:
7565+
case ARM::MVE_VQDMLADHs32:
7566+
case ARM::MVE_VQDMLADHXs32:
7567+
case ARM::MVE_VQRDMLADHs32:
7568+
case ARM::MVE_VQRDMLADHXs32:
7569+
case ARM::MVE_VQDMLSDHs32:
7570+
case ARM::MVE_VQDMLSDHXs32:
7571+
case ARM::MVE_VQRDMLSDHs32:
7572+
case ARM::MVE_VQRDMLSDHXs32: {
7573+
if (Operands[3]->getReg() == Operands[4]->getReg()) {
7574+
return Error (Operands[3]->getStartLoc(),
7575+
"Qd register and Qn register can't be identical");
7576+
}
7577+
if (Operands[3]->getReg() == Operands[5]->getReg()) {
7578+
return Error (Operands[3]->getStartLoc(),
7579+
"Qd register and Qm register can't be identical");
7580+
}
7581+
break;
7582+
}
75447583
}
75457584

75467585
return false;

‎llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -312,6 +312,8 @@ static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
312312
uint64_t Address, const void *Decoder);
313313
static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst,unsigned Val,
314314
uint64_t Address, const void *Decoder);
315+
static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
316+
uint64_t Address, const void *Decoder);
315317
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
316318
uint64_t Address, const void *Decoder);
317319
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
@@ -3462,6 +3464,31 @@ DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
34623464
return S;
34633465
}
34643466

3467+
static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
3468+
uint64_t Address, const void *Decoder) {
3469+
DecodeStatus S = MCDisassembler::Success;
3470+
3471+
unsigned Qd = fieldFromInstruction(Insn, 13, 3);
3472+
Qd |= fieldFromInstruction(Insn, 22, 1) << 3;
3473+
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3474+
return MCDisassembler::Fail;
3475+
Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3476+
3477+
unsigned Qn = fieldFromInstruction(Insn, 17, 3);
3478+
Qn |= fieldFromInstruction(Insn, 7, 1) << 3;
3479+
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3480+
return MCDisassembler::Fail;
3481+
unsigned Qm = fieldFromInstruction(Insn, 1, 3);
3482+
Qm |= fieldFromInstruction(Insn, 5, 1) << 3;
3483+
if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3484+
return MCDisassembler::Fail;
3485+
if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR
3486+
Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3487+
Inst.addOperand(MCOperand::createImm(Qd));
3488+
3489+
return S;
3490+
}
3491+
34653492
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
34663493
uint64_t Address, const void *Decoder) {
34673494
DecodeStatus S = MCDisassembler::Success;

‎llvm/test/MC/ARM/mve-qdest-qsrc.s

Lines changed: 541 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,541 @@
1+
# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \
2+
# RUN: | FileCheck --check-prefix=CHECK-NOFP %s
3+
# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
4+
# RUN: | FileCheck --check-prefix=CHECK %s
5+
# RUN: FileCheck --check-prefix=ERROR < %t %s
6+
7+
# CHECK: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
8+
# CHECK-NOFP-NOT: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
9+
vcvtb.f16.f32 q1, q4
10+
11+
# CHECK: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
12+
# CHECK-NOFP-NOT: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
13+
vcvtt.f32.f16 q0, q1
14+
15+
# CHECK: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
16+
# CHECK-NOFP-NOT: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
17+
vcvtt.f64.f16 d0, s0
18+
19+
# CHECK: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
20+
# CHECK-NOFP-NOT: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
21+
vcvtt.f16.f64 s1, d2
22+
23+
# CHECK: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
24+
# CHECK-NOFP-NOT: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
25+
vcvtt.f16.f32 q1, q4
26+
27+
# CHECK: vqdmladhx.s8 q1, q6, q6 @ encoding: [0x0c,0xee,0x0c,0x3e]
28+
# CHECK-NOFP: vqdmladhx.s8 q1, q6, q6 @ encoding: [0x0c,0xee,0x0c,0x3e]
29+
vqdmladhx.s8 q1, q6, q6
30+
31+
# CHECK: vqdmladhx.s16 q0, q1, q4 @ encoding: [0x12,0xee,0x08,0x1e]
32+
# CHECK-NOFP: vqdmladhx.s16 q0, q1, q4 @ encoding: [0x12,0xee,0x08,0x1e]
33+
vqdmladhx.s16 q0, q1, q4
34+
35+
# CHECK: vqdmladhx.s32 q0, q3, q7 @ encoding: [0x26,0xee,0x0e,0x1e]
36+
# CHECK-NOFP: vqdmladhx.s32 q0, q3, q7 @ encoding: [0x26,0xee,0x0e,0x1e]
37+
vqdmladhx.s32 q0, q3, q7
38+
39+
# CHECK: vqdmladh.s8 q0, q1, q1 @ encoding: [0x02,0xee,0x02,0x0e]
40+
# CHECK-NOFP: vqdmladh.s8 q0, q1, q1 @ encoding: [0x02,0xee,0x02,0x0e]
41+
vqdmladh.s8 q0, q1, q1
42+
43+
# CHECK: vqdmladh.s16 q0, q2, q2 @ encoding: [0x14,0xee,0x04,0x0e]
44+
# CHECK-NOFP: vqdmladh.s16 q0, q2, q2 @ encoding: [0x14,0xee,0x04,0x0e]
45+
vqdmladh.s16 q0, q2, q2
46+
47+
# CHECK: vqdmladh.s32 q1, q5, q7 @ encoding: [0x2a,0xee,0x0e,0x2e]
48+
# CHECK-NOFP: vqdmladh.s32 q1, q5, q7 @ encoding: [0x2a,0xee,0x0e,0x2e]
49+
vqdmladh.s32 q1, q5, q7
50+
51+
# CHECK: vqrdmladhx.s8 q0, q7, q0 @ encoding: [0x0e,0xee,0x01,0x1e]
52+
# CHECK-NOFP: vqrdmladhx.s8 q0, q7, q0 @ encoding: [0x0e,0xee,0x01,0x1e]
53+
vqrdmladhx.s8 q0, q7, q0
54+
55+
# CHECK: vqrdmladhx.s16 q0, q0, q1 @ encoding: [0x10,0xee,0x03,0x1e]
56+
# CHECK-NOFP: vqrdmladhx.s16 q0, q0, q1 @ encoding: [0x10,0xee,0x03,0x1e]
57+
vqrdmladhx.s16 q0, q0, q1
58+
59+
# CHECK: vqrdmladhx.s32 q1, q0, q4 @ encoding: [0x20,0xee,0x09,0x3e]
60+
# CHECK-NOFP: vqrdmladhx.s32 q1, q0, q4 @ encoding: [0x20,0xee,0x09,0x3e]
61+
vqrdmladhx.s32 q1, q0, q4
62+
63+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
64+
vqrdmladhx.s32 q1, q1, q0
65+
66+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
67+
vqrdmladhx.s32 q1, q0, q1
68+
69+
# CHECK: vqrdmladh.s8 q0, q6, q2 @ encoding: [0x0c,0xee,0x05,0x0e]
70+
# CHECK-NOFP: vqrdmladh.s8 q0, q6, q2 @ encoding: [0x0c,0xee,0x05,0x0e]
71+
vqrdmladh.s8 q0, q6, q2
72+
73+
# CHECK: vqrdmladh.s16 q1, q5, q4 @ encoding: [0x1a,0xee,0x09,0x2e]
74+
# CHECK-NOFP: vqrdmladh.s16 q1, q5, q4 @ encoding: [0x1a,0xee,0x09,0x2e]
75+
vqrdmladh.s16 q1, q5, q4
76+
77+
# CHECK: vqrdmladh.s32 q0, q2, q2 @ encoding: [0x24,0xee,0x05,0x0e]
78+
# CHECK-NOFP: vqrdmladh.s32 q0, q2, q2 @ encoding: [0x24,0xee,0x05,0x0e]
79+
vqrdmladh.s32 q0, q2, q2
80+
81+
# CHECK: vqdmlsdhx.s8 q1, q4, q7 @ encoding: [0x08,0xfe,0x0e,0x3e]
82+
# CHECK-NOFP: vqdmlsdhx.s8 q1, q4, q7 @ encoding: [0x08,0xfe,0x0e,0x3e]
83+
vqdmlsdhx.s8 q1, q4, q7
84+
85+
# CHECK: vqdmlsdhx.s16 q0, q2, q5 @ encoding: [0x14,0xfe,0x0a,0x1e]
86+
# CHECK-NOFP: vqdmlsdhx.s16 q0, q2, q5 @ encoding: [0x14,0xfe,0x0a,0x1e]
87+
vqdmlsdhx.s16 q0, q2, q5
88+
89+
# CHECK: vqdmlsdhx.s32 q3, q4, q6 @ encoding: [0x28,0xfe,0x0c,0x7e]
90+
# CHECK-NOFP: vqdmlsdhx.s32 q3, q4, q6 @ encoding: [0x28,0xfe,0x0c,0x7e]
91+
vqdmlsdhx.s32 q3, q4, q6
92+
93+
# CHECK: vqdmlsdh.s8 q0, q3, q6 @ encoding: [0x06,0xfe,0x0c,0x0e]
94+
# CHECK-NOFP: vqdmlsdh.s8 q0, q3, q6 @ encoding: [0x06,0xfe,0x0c,0x0e]
95+
vqdmlsdh.s8 q0, q3, q6
96+
97+
# CHECK: vqdmlsdh.s16 q0, q4, q1 @ encoding: [0x18,0xfe,0x02,0x0e]
98+
# CHECK-NOFP: vqdmlsdh.s16 q0, q4, q1 @ encoding: [0x18,0xfe,0x02,0x0e]
99+
vqdmlsdh.s16 q0, q4, q1
100+
101+
# CHECK: vqdmlsdh.s32 q2, q5, q0 @ encoding: [0x2a,0xfe,0x00,0x4e]
102+
# CHECK-NOFP: vqdmlsdh.s32 q2, q5, q0 @ encoding: [0x2a,0xfe,0x00,0x4e]
103+
vqdmlsdh.s32 q2, q5, q0
104+
105+
# CHECK: vqrdmlsdhx.s8 q0, q3, q1 @ encoding: [0x06,0xfe,0x03,0x1e]
106+
# CHECK-NOFP: vqrdmlsdhx.s8 q0, q3, q1 @ encoding: [0x06,0xfe,0x03,0x1e]
107+
vqrdmlsdhx.s8 q0, q3, q1
108+
109+
# CHECK: vqrdmlsdhx.s16 q0, q1, q4 @ encoding: [0x12,0xfe,0x09,0x1e]
110+
# CHECK-NOFP: vqrdmlsdhx.s16 q0, q1, q4 @ encoding: [0x12,0xfe,0x09,0x1e]
111+
vqrdmlsdhx.s16 q0, q1, q4
112+
113+
# CHECK: vqrdmlsdhx.s32 q1, q6, q3 @ encoding: [0x2c,0xfe,0x07,0x3e]
114+
# CHECK-NOFP: vqrdmlsdhx.s32 q1, q6, q3 @ encoding: [0x2c,0xfe,0x07,0x3e]
115+
vqrdmlsdhx.s32 q1, q6, q3
116+
117+
# CHECK: vqrdmlsdh.s8 q3, q3, q0 @ encoding: [0x06,0xfe,0x01,0x6e]
118+
# CHECK-NOFP: vqrdmlsdh.s8 q3, q3, q0 @ encoding: [0x06,0xfe,0x01,0x6e]
119+
vqrdmlsdh.s8 q3, q3, q0
120+
121+
# CHECK: vqrdmlsdh.s16 q0, q7, q4 @ encoding: [0x1e,0xfe,0x09,0x0e]
122+
# CHECK-NOFP: vqrdmlsdh.s16 q0, q7, q4 @ encoding: [0x1e,0xfe,0x09,0x0e]
123+
vqrdmlsdh.s16 q0, q7, q4
124+
125+
# CHECK: vqrdmlsdh.s32 q0, q6, q7 @ encoding: [0x2c,0xfe,0x0f,0x0e]
126+
# CHECK-NOFP: vqrdmlsdh.s32 q0, q6, q7 @ encoding: [0x2c,0xfe,0x0f,0x0e]
127+
vqrdmlsdh.s32 q0, q6, q7
128+
129+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
130+
vqrdmlsdh.s32 q0, q0, q7
131+
132+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
133+
vqrdmlsdh.s32 q0, q6, q0
134+
135+
# CHECK: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]
136+
# CHECK-NOFP-NOT: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]
137+
vcmul.f16 q0, q1, q2, #90
138+
139+
# CHECK: vcmul.f16 q6, q2, q5, #0 @ encoding: [0x34,0xee,0x0a,0xce]
140+
# CHECK-NOFP-NOT: vcmul.f16 q6, q2, q5, #0 @ encoding: [0x34,0xee,0x0a,0xce]
141+
vcmul.f16 q6, q2, q5, #0
142+
143+
# CHECK: vcmul.f16 q1, q0, q5, #90 @ encoding: [0x30,0xee,0x0b,0x2e]
144+
# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #90 @ encoding: [0x30,0xee,0x0b,0x2e]
145+
vcmul.f16 q1, q0, q5, #90
146+
147+
# CHECK: vcmul.f16 q1, q0, q5, #180 @ encoding: [0x30,0xee,0x0a,0x3e]
148+
# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #180 @ encoding: [0x30,0xee,0x0a,0x3e]
149+
vcmul.f16 q1, q0, q5, #180
150+
151+
# CHECK: vcmul.f16 q1, q0, q5, #270 @ encoding: [0x30,0xee,0x0b,0x3e]
152+
# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q5, #270 @ encoding: [0x30,0xee,0x0b,0x3e]
153+
vcmul.f16 q1, q0, q5, #270
154+
155+
# CHECK: vcmul.f16 q1, q0, q1, #270 @ encoding: [0x30,0xee,0x03,0x3e]
156+
# CHECK-NOFP-NOT: vcmul.f16 q1, q0, q1, #270 @ encoding: [0x30,0xee,0x03,0x3e]
157+
vcmul.f16 q1, q0, q1, #270
158+
159+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 0, 90, 180 or 270
160+
vcmul.f16 q1, q0, q5, #300
161+
162+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
163+
vcmul.f32 q1, q1, q5, #0
164+
165+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
166+
vcmul.f32 q1, q5, q1, #0
167+
168+
# CHECK: vcmul.f32 q1, q7, q5, #0 @ encoding: [0x3e,0xfe,0x0a,0x2e]
169+
# CHECK-NOFP-NOT: vcmul.f32 q1, q7, q5, #0 @ encoding: [0x3e,0xfe,0x0a,0x2e]
170+
vcmul.f32 q1, q7, q5, #0
171+
172+
# CHECK: vcmul.f32 q3, q4, q2, #90 @ encoding: [0x38,0xfe,0x05,0x6e]
173+
# CHECK-NOFP-NOT: vcmul.f32 q3, q4, q2, #90 @ encoding: [0x38,0xfe,0x05,0x6e]
174+
vcmul.f32 q3, q4, q2, #90
175+
176+
# CHECK: vcmul.f32 q5, q1, q3, #180 @ encoding: [0x32,0xfe,0x06,0xbe]
177+
# CHECK-NOFP-NOT: vcmul.f32 q5, q1, q3, #180 @ encoding: [0x32,0xfe,0x06,0xbe]
178+
vcmul.f32 q5, q1, q3, #180
179+
180+
# CHECK: vcmul.f32 q0, q7, q4, #270 @ encoding: [0x3e,0xfe,0x09,0x1e]
181+
# CHECK-NOFP-NOT: vcmul.f32 q0, q7, q4, #270 @ encoding: [0x3e,0xfe,0x09,0x1e]
182+
vcmul.f32 q0, q7, q4, #270
183+
184+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 0, 90, 180 or 270
185+
vcmul.f32 q1, q0, q5, #300
186+
187+
# CHECK: vmullb.s8 q2, q6, q0 @ encoding: [0x0d,0xee,0x00,0x4e]
188+
# CHECK-NOFP: vmullb.s8 q2, q6, q0 @ encoding: [0x0d,0xee,0x00,0x4e]
189+
vmullb.s8 q2, q6, q0
190+
191+
# CHECK: vmullb.s16 q3, q4, q3 @ encoding: [0x19,0xee,0x06,0x6e]
192+
# CHECK-NOFP: vmullb.s16 q3, q4, q3 @ encoding: [0x19,0xee,0x06,0x6e]
193+
vmullb.s16 q3, q4, q3
194+
195+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
196+
vmullb.s32 q3, q4, q3
197+
198+
# CHECK: vmullb.s32 q3, q5, q6 @ encoding: [0x2b,0xee,0x0c,0x6e]
199+
# CHECK-NOFP: vmullb.s32 q3, q5, q6 @ encoding: [0x2b,0xee,0x0c,0x6e]
200+
vmullb.s32 q3, q5, q6
201+
202+
# CHECK: vmullt.s8 q0, q6, q2 @ encoding: [0x0d,0xee,0x04,0x1e]
203+
# CHECK-NOFP: vmullt.s8 q0, q6, q2 @ encoding: [0x0d,0xee,0x04,0x1e]
204+
vmullt.s8 q0, q6, q2
205+
206+
# CHECK: vmullt.s16 q0, q0, q2 @ encoding: [0x11,0xee,0x04,0x1e]
207+
# CHECK-NOFP: vmullt.s16 q0, q0, q2 @ encoding: [0x11,0xee,0x04,0x1e]
208+
vmullt.s16 q0, q0, q2
209+
210+
# CHECK: vmullt.s32 q2, q4, q4 @ encoding: [0x29,0xee,0x08,0x5e]
211+
# CHECK-NOFP: vmullt.s32 q2, q4, q4 @ encoding: [0x29,0xee,0x08,0x5e]
212+
vmullt.s32 q2, q4, q4
213+
214+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
215+
vmullt.s32 q4, q4, q2
216+
217+
# CHECK: vmullb.p8 q2, q3, q7 @ encoding: [0x37,0xee,0x0e,0x4e]
218+
# CHECK-NOFP: vmullb.p8 q2, q3, q7 @ encoding: [0x37,0xee,0x0e,0x4e]
219+
vmullb.p8 q2, q3, q7
220+
221+
# CHECK: vmullb.p16 q0, q1, q3 @ encoding: [0x33,0xfe,0x06,0x0e]
222+
# CHECK-NOFP: vmullb.p16 q0, q1, q3 @ encoding: [0x33,0xfe,0x06,0x0e]
223+
vmullb.p16 q0, q1, q3
224+
225+
# CHECK: vmullt.p8 q1, q1, q7 @ encoding: [0x33,0xee,0x0e,0x3e]
226+
# CHECK-NOFP: vmullt.p8 q1, q1, q7 @ encoding: [0x33,0xee,0x0e,0x3e]
227+
vmullt.p8 q1, q1, q7
228+
229+
# CHECK: vmullt.p16 q0, q7, q7 @ encoding: [0x3f,0xfe,0x0e,0x1e]
230+
# CHECK-NOFP: vmullt.p16 q0, q7, q7 @ encoding: [0x3f,0xfe,0x0e,0x1e]
231+
vmullt.p16 q0, q7, q7
232+
233+
# CHECK: vmulh.s8 q0, q4, q5 @ encoding: [0x09,0xee,0x0b,0x0e]
234+
# CHECK-NOFP: vmulh.s8 q0, q4, q5 @ encoding: [0x09,0xee,0x0b,0x0e]
235+
vmulh.s8 q0, q4, q5
236+
237+
# CHECK: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
238+
# CHECK-NOFP: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
239+
vmulh.s16 q0, q7, q4
240+
241+
# CHECK: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
242+
# CHECK-NOFP: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
243+
vmulh.s32 q0, q7, q4
244+
245+
# CHECK: vmulh.u8 q3, q5, q2 @ encoding: [0x0b,0xfe,0x05,0x6e]
246+
# CHECK-NOFP: vmulh.u8 q3, q5, q2 @ encoding: [0x0b,0xfe,0x05,0x6e]
247+
vmulh.u8 q3, q5, q2
248+
249+
# CHECK: vmulh.u16 q2, q7, q4 @ encoding: [0x1f,0xfe,0x09,0x4e]
250+
# CHECK-NOFP: vmulh.u16 q2, q7, q4 @ encoding: [0x1f,0xfe,0x09,0x4e]
251+
vmulh.u16 q2, q7, q4
252+
253+
# CHECK: vmulh.u32 q1, q3, q2 @ encoding: [0x27,0xfe,0x05,0x2e]
254+
# CHECK-NOFP: vmulh.u32 q1, q3, q2 @ encoding: [0x27,0xfe,0x05,0x2e]
255+
vmulh.u32 q1, q3, q2
256+
257+
# CHECK: vrmulh.s8 q1, q1, q2 @ encoding: [0x03,0xee,0x05,0x3e]
258+
# CHECK-NOFP: vrmulh.s8 q1, q1, q2 @ encoding: [0x03,0xee,0x05,0x3e]
259+
vrmulh.s8 q1, q1, q2
260+
261+
# CHECK: vrmulh.s16 q1, q1, q2 @ encoding: [0x13,0xee,0x05,0x3e]
262+
# CHECK-NOFP: vrmulh.s16 q1, q1, q2 @ encoding: [0x13,0xee,0x05,0x3e]
263+
vrmulh.s16 q1, q1, q2
264+
265+
# CHECK: vrmulh.s32 q3, q1, q0 @ encoding: [0x23,0xee,0x01,0x7e]
266+
# CHECK-NOFP: vrmulh.s32 q3, q1, q0 @ encoding: [0x23,0xee,0x01,0x7e]
267+
vrmulh.s32 q3, q1, q0
268+
269+
# CHECK: vrmulh.u8 q1, q6, q0 @ encoding: [0x0d,0xfe,0x01,0x3e]
270+
# CHECK-NOFP: vrmulh.u8 q1, q6, q0 @ encoding: [0x0d,0xfe,0x01,0x3e]
271+
vrmulh.u8 q1, q6, q0
272+
273+
# CHECK: vrmulh.u16 q4, q3, q6 @ encoding: [0x17,0xfe,0x0d,0x9e]
274+
# CHECK-NOFP: vrmulh.u16 q4, q3, q6 @ encoding: [0x17,0xfe,0x0d,0x9e]
275+
vrmulh.u16 q4, q3, q6
276+
277+
# CHECK: vrmulh.u32 q1, q2, q2 @ encoding: [0x25,0xfe,0x05,0x3e]
278+
# CHECK-NOFP: vrmulh.u32 q1, q2, q2 @ encoding: [0x25,0xfe,0x05,0x3e]
279+
vrmulh.u32 q1, q2, q2
280+
281+
# CHECK: vqmovnb.s16 q0, q1 @ encoding: [0x33,0xee,0x03,0x0e]
282+
# CHECK-NOFP: vqmovnb.s16 q0, q1 @ encoding: [0x33,0xee,0x03,0x0e]
283+
vqmovnb.s16 q0, q1
284+
285+
# CHECK: vqmovnt.s16 q2, q0 @ encoding: [0x33,0xee,0x01,0x5e]
286+
# CHECK-NOFP: vqmovnt.s16 q2, q0 @ encoding: [0x33,0xee,0x01,0x5e]
287+
vqmovnt.s16 q2, q0
288+
289+
# CHECK: vqmovnb.s32 q0, q5 @ encoding: [0x37,0xee,0x0b,0x0e]
290+
# CHECK-NOFP: vqmovnb.s32 q0, q5 @ encoding: [0x37,0xee,0x0b,0x0e]
291+
vqmovnb.s32 q0, q5
292+
293+
# CHECK: vqmovnt.s32 q0, q1 @ encoding: [0x37,0xee,0x03,0x1e]
294+
# CHECK-NOFP: vqmovnt.s32 q0, q1 @ encoding: [0x37,0xee,0x03,0x1e]
295+
vqmovnt.s32 q0, q1
296+
297+
# CHECK: vqmovnb.u16 q0, q4 @ encoding: [0x33,0xfe,0x09,0x0e]
298+
# CHECK-NOFP: vqmovnb.u16 q0, q4 @ encoding: [0x33,0xfe,0x09,0x0e]
299+
vqmovnb.u16 q0, q4
300+
301+
# CHECK: vqmovnt.u16 q0, q7 @ encoding: [0x33,0xfe,0x0f,0x1e]
302+
# CHECK-NOFP: vqmovnt.u16 q0, q7 @ encoding: [0x33,0xfe,0x0f,0x1e]
303+
vqmovnt.u16 q0, q7
304+
305+
# CHECK: vqmovnb.u32 q0, q4 @ encoding: [0x37,0xfe,0x09,0x0e]
306+
# CHECK-NOFP: vqmovnb.u32 q0, q4 @ encoding: [0x37,0xfe,0x09,0x0e]
307+
vqmovnb.u32 q0, q4
308+
309+
# CHECK: vqmovnt.u32 q0, q2 @ encoding: [0x37,0xfe,0x05,0x1e]
310+
# CHECK-NOFP: vqmovnt.u32 q0, q2 @ encoding: [0x37,0xfe,0x05,0x1e]
311+
vqmovnt.u32 q0, q2
312+
313+
# CHECK: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
314+
# CHECK-NOFP-NOT: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
315+
vcvtb.f16.f32 q1, q4
316+
317+
# CHECK: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
318+
# CHECK-NOFP-NOT: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
319+
vcvtt.f16.f32 q1, q4
320+
321+
# CHECK: vcvtb.f32.f16 q0, q3 @ encoding: [0x3f,0xfe,0x07,0x0e]
322+
# CHECK-NOFP-NOT: vcvtb.f32.f16 q0, q3 @ encoding: [0x3f,0xfe,0x07,0x0e]
323+
vcvtb.f32.f16 q0, q3
324+
325+
# CHECK: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
326+
# CHECK-NOFP-NOT: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
327+
vcvtt.f32.f16 q0, q1
328+
329+
# CHECK: vqmovunb.s16 q0, q3 @ encoding: [0x31,0xee,0x87,0x0e]
330+
# CHECK-NOFP: vqmovunb.s16 q0, q3 @ encoding: [0x31,0xee,0x87,0x0e]
331+
vqmovunb.s16 q0, q3
332+
333+
# CHECK: vqmovunt.s16 q4, q1 @ encoding: [0x31,0xee,0x83,0x9e]
334+
# CHECK-NOFP: vqmovunt.s16 q4, q1 @ encoding: [0x31,0xee,0x83,0x9e]
335+
vqmovunt.s16 q4, q1
336+
337+
# CHECK: vqmovunb.s32 q1, q7 @ encoding: [0x35,0xee,0x8f,0x2e]
338+
# CHECK-NOFP: vqmovunb.s32 q1, q7 @ encoding: [0x35,0xee,0x8f,0x2e]
339+
vqmovunb.s32 q1, q7
340+
341+
# CHECK: vqmovunt.s32 q0, q2 @ encoding: [0x35,0xee,0x85,0x1e]
342+
# CHECK-NOFP: vqmovunt.s32 q0, q2 @ encoding: [0x35,0xee,0x85,0x1e]
343+
vqmovunt.s32 q0, q2
344+
345+
# CHECK: vmovnb.i16 q1, q5 @ encoding: [0x31,0xfe,0x8b,0x2e]
346+
# CHECK-NOFP: vmovnb.i16 q1, q5 @ encoding: [0x31,0xfe,0x8b,0x2e]
347+
vmovnb.i16 q1, q5
348+
349+
# CHECK: vmovnt.i16 q0, q0 @ encoding: [0x31,0xfe,0x81,0x1e]
350+
# CHECK-NOFP: vmovnt.i16 q0, q0 @ encoding: [0x31,0xfe,0x81,0x1e]
351+
vmovnt.i16 q0, q0
352+
353+
# CHECK: vmovnb.i32 q1, q0 @ encoding: [0x35,0xfe,0x81,0x2e]
354+
# CHECK-NOFP: vmovnb.i32 q1, q0 @ encoding: [0x35,0xfe,0x81,0x2e]
355+
vmovnb.i32 q1, q0
356+
357+
# CHECK: vmovnt.i32 q3, q3 @ encoding: [0x35,0xfe,0x87,0x7e]
358+
# CHECK-NOFP: vmovnt.i32 q3, q3 @ encoding: [0x35,0xfe,0x87,0x7e]
359+
vmovnt.i32 q3, q3
360+
361+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
362+
vhcadd.s8 q3, q7, q5, #0
363+
364+
# CHECK: vhcadd.s8 q3, q7, q5, #90 @ encoding: [0x0e,0xee,0x0a,0x6f]
365+
# CHECK-NOFP: vhcadd.s8 q3, q7, q5, #90 @ encoding: [0x0e,0xee,0x0a,0x6f]
366+
vhcadd.s8 q3, q7, q5, #90
367+
368+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
369+
vhcadd.s8 q3, q7, q5, #0
370+
371+
# CHECK: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
372+
# CHECK-NOFP: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
373+
vhcadd.s16 q0, q0, q6, #90
374+
375+
# CHECK: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
376+
# CHECK-NOFP: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
377+
vhcadd.s16 q0, q0, q6, #90
378+
379+
# CHECK: vhcadd.s16 q3, q1, q0, #270 @ encoding: [0x12,0xee,0x00,0x7f]
380+
# CHECK-NOFP: vhcadd.s16 q3, q1, q0, #270 @ encoding: [0x12,0xee,0x00,0x7f]
381+
vhcadd.s16 q3, q1, q0, #270
382+
383+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
384+
vhcadd.s32 q3, q4, q5, #0
385+
386+
# CHECK: vhcadd.s32 q3, q4, q5, #90 @ encoding: [0x28,0xee,0x0a,0x6f]
387+
# CHECK-NOFP: vhcadd.s32 q3, q4, q5, #90 @ encoding: [0x28,0xee,0x0a,0x6f]
388+
vhcadd.s32 q3, q4, q5, #90
389+
390+
# CHECK: vhcadd.s32 q6, q7, q2, #270 @ encoding: [0x2e,0xee,0x04,0xdf]
391+
# CHECK-NOFP: vhcadd.s32 q6, q7, q2, #270 @ encoding: [0x2e,0xee,0x04,0xdf]
392+
vhcadd.s32 q6, q7, q2, #270
393+
394+
# CHECK: vadc.i32 q1, q0, q2 @ encoding: [0x30,0xee,0x04,0x2f]
395+
# CHECK-NOFP: vadc.i32 q1, q0, q2 @ encoding: [0x30,0xee,0x04,0x2f]
396+
vadc.i32 q1, q0, q2
397+
398+
# CHECK: vadci.i32 q0, q1, q1 @ encoding: [0x32,0xee,0x02,0x1f]
399+
# CHECK-NOFP: vadci.i32 q0, q1, q1 @ encoding: [0x32,0xee,0x02,0x1f]
400+
vadci.i32 q0, q1, q1
401+
402+
# CHECK: vcadd.i8 q1, q0, q2, #90 @ encoding: [0x00,0xfe,0x04,0x2f]
403+
# CHECK-NOFP: vcadd.i8 q1, q0, q2, #90 @ encoding: [0x00,0xfe,0x04,0x2f]
404+
vcadd.i8 q1, q0, q2, #90
405+
406+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
407+
vcadd.i8 q1, q0, q2, #0
408+
409+
# CHECK: vcadd.i16 q0, q2, q3, #90 @ encoding: [0x14,0xfe,0x06,0x0f]
410+
# CHECK-NOFP: vcadd.i16 q0, q2, q3, #90 @ encoding: [0x14,0xfe,0x06,0x0f]
411+
vcadd.i16 q0, q2, q3, #90
412+
413+
# CHECK: vcadd.i16 q0, q5, q5, #270 @ encoding: [0x1a,0xfe,0x0a,0x1f]
414+
# CHECK-NOFP: vcadd.i16 q0, q5, q5, #270 @ encoding: [0x1a,0xfe,0x0a,0x1f]
415+
vcadd.i16 q0, q5, q5, #270
416+
417+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
418+
vcadd.i16 q1, q0, q2, #0
419+
420+
# CHECK: vcadd.i32 q4, q2, q5, #90 @ encoding: [0x24,0xfe,0x0a,0x8f]
421+
# CHECK-NOFP: vcadd.i32 q4, q2, q5, #90 @ encoding: [0x24,0xfe,0x0a,0x8f]
422+
vcadd.i32 q4, q2, q5, #90
423+
424+
# CHECK: vcadd.i32 q5, q5, q0, #270 @ encoding: [0x2a,0xfe,0x00,0xbf]
425+
# CHECK-NOFP: vcadd.i32 q5, q5, q0, #270 @ encoding: [0x2a,0xfe,0x00,0xbf]
426+
vcadd.i32 q5, q5, q0, #270
427+
428+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
429+
vcadd.i32 q4, q2, q5, #0
430+
431+
# CHECK: vsbc.i32 q3, q1, q1 @ encoding: [0x32,0xfe,0x02,0x6f]
432+
# CHECK-NOFP: vsbc.i32 q3, q1, q1 @ encoding: [0x32,0xfe,0x02,0x6f]
433+
vsbc.i32 q3, q1, q1
434+
435+
# CHECK: vsbci.i32 q2, q6, q2 @ encoding: [0x3c,0xfe,0x04,0x5f]
436+
# CHECK-NOFP: vsbci.i32 q2, q6, q2 @ encoding: [0x3c,0xfe,0x04,0x5f]
437+
vsbci.i32 q2, q6, q2
438+
439+
# CHECK: vqdmullb.s16 q0, q4, q5 @ encoding: [0x38,0xee,0x0b,0x0f]
440+
# CHECK-NOFP: vqdmullb.s16 q0, q4, q5 @ encoding: [0x38,0xee,0x0b,0x0f]
441+
vqdmullb.s16 q0, q4, q5
442+
443+
# CHECK: vqdmullt.s16 q0, q6, q5 @ encoding: [0x3c,0xee,0x0b,0x1f]
444+
# CHECK-NOFP: vqdmullt.s16 q0, q6, q5 @ encoding: [0x3c,0xee,0x0b,0x1f]
445+
vqdmullt.s16 q0, q6, q5
446+
447+
# CHECK: vqdmullb.s32 q0, q3, q7 @ encoding: [0x36,0xfe,0x0f,0x0f]
448+
# CHECK-NOFP: vqdmullb.s32 q0, q3, q7 @ encoding: [0x36,0xfe,0x0f,0x0f]
449+
vqdmullb.s32 q0, q3, q7
450+
451+
# CHECK: vqdmullt.s32 q0, q7, q5 @ encoding: [0x3e,0xfe,0x0b,0x1f]
452+
# CHECK-NOFP: vqdmullt.s32 q0, q7, q5 @ encoding: [0x3e,0xfe,0x0b,0x1f]
453+
vqdmullt.s32 q0, q7, q5
454+
455+
# CHECK: vqdmullb.s16 q0, q1, q0 @ encoding: [0x32,0xee,0x01,0x0f]
456+
# CHECK-NOFP: vqdmullb.s16 q0, q1, q0 @ encoding: [0x32,0xee,0x01,0x0f]
457+
vqdmullb.s16 q0, q1, q0
458+
459+
# CHECK: vqdmullt.s16 q0, q0, q5 @ encoding: [0x30,0xee,0x0b,0x1f]
460+
# CHECK-NOFP: vqdmullt.s16 q0, q0, q5 @ encoding: [0x30,0xee,0x0b,0x1f]
461+
vqdmullt.s16 q0, q0, q5
462+
463+
# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
464+
vqdmullb.s32 q0, q1, q0
465+
466+
vqdmullt.s16 q0, q1, q2
467+
# CHECK: vqdmullt.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x1f]
468+
# CHECK-NOFP: vqdmullt.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x1f]
469+
470+
vpste
471+
vqdmulltt.s32 q0, q1, q2
472+
vqdmullbe.s16 q0, q1, q2
473+
# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
474+
# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
475+
# CHECK: vqdmulltt.s32 q0, q1, q2 @ encoding: [0x32,0xfe,0x05,0x1f]
476+
# CHECK-NOFP: vqdmulltt.s32 q0, q1, q2 @ encoding: [0x32,0xfe,0x05,0x1f]
477+
# CHECK: vqdmullbe.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x0f]
478+
# CHECK-NOFP: vqdmullbe.s16 q0, q1, q2 @ encoding: [0x32,0xee,0x05,0x0f]
479+
480+
vpste
481+
vmulltt.p8 q0, q1, q2
482+
vmullbe.p16 q0, q1, q2
483+
# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
484+
# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
485+
# CHECK: vmulltt.p8 q0, q1, q2 @ encoding: [0x33,0xee,0x04,0x1e]
486+
# CHECK-NOFP: vmulltt.p8 q0, q1, q2 @ encoding: [0x33,0xee,0x04,0x1e]
487+
# CHECK: vmullbe.p16 q0, q1, q2 @ encoding: [0x33,0xfe,0x04,0x0e]
488+
# CHECK-NOFP: vmullbe.p16 q0, q1, q2 @ encoding: [0x33,0xfe,0x04,0x0e]
489+
490+
# ----------------------------------------------------------------------
491+
# The following tests have to go last because of the NOFP-NOT checks inside the
492+
# VPT block.
493+
494+
vpste
495+
vcmult.f16 q0, q1, q2, #180
496+
vcmule.f16 q0, q1, q2, #180
497+
# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
498+
# CHECK: vcmult.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
499+
# CHECK-NOFP-NOT: vcmult.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
500+
# CHECK: vcmule.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
501+
# CHECK-NOFP-NOT: vcmule.f16 q0, q1, q2, #180 @ encoding: [0x32,0xee,0x04,0x1e]
502+
503+
vpstet
504+
vcvtbt.f16.f32 q0, q1
505+
vcvtne.s16.f16 q0, q1
506+
vcvtmt.s16.f16 q0, q1
507+
# CHECK: vpstet @ encoding: [0x71,0xfe,0x4d,0xcf]
508+
# CHECK: vcvtbt.f16.f32 q0, q1 @ encoding: [0x3f,0xee,0x03,0x0e]
509+
# CHECK-NOFP-NOT: vcvtbt.f16.f32 q0, q1 @ encoding: [0x3f,0xee,0x03,0x0e]
510+
# CHECK: vcvtne.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x01]
511+
# CHECK-NOFP-NOT: vcvtne.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x01]
512+
# CHECK: vcvtmt.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x03
513+
# CHECK-NOFP-NOT: vcvtmt.s16.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x03
514+
515+
vpte.f32 lt, q3, r1
516+
vcvttt.f16.f32 q2, q0
517+
vcvtte.f32.f16 q1, q0
518+
# CHECK: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xc1,0x9f]
519+
# CHECK-NOFP-NOT: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xe1,0x8f]
520+
# CHECK: vcvttt.f16.f32 q2, q0 @ encoding: [0x3f,0xee,0x01,0x5e]
521+
# CHECK-NOFP-NOT: vcvttt.f16.f32 q2, q0 @ encoding: [0x3f,0xee,0x01,0x5e]
522+
# CHECK: vcvtte.f32.f16 q1, q0 @ encoding: [0x3f,0xfe,0x01,0x3e]
523+
524+
vpte.f32 lt, q3, r1
525+
vcvtbt.f16.f32 q2, q0
526+
vcvtbe.f32.f16 q1, q0
527+
# CHECK: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xc1,0x9f]
528+
# CHECK-NOFP-NOT: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xe1,0x8f]
529+
# CHECK: vcvtbt.f16.f32 q2, q0 @ encoding: [0x3f,0xee,0x01,0x4e]
530+
# CHECK-NOFP-NOT: vcvtbt.f16.f32 q2, q0 @ encoding: [0x3f,0xee,0x01,0x4e]
531+
# CHECK: vcvtbe.f32.f16 q1, q0 @ encoding: [0x3f,0xfe,0x01,0x2e]
532+
# CHECK-NOFP-NOT: vcvtbe.f32.f16 q1, q0 @ encoding: [0x3f,0xfe,0x01,0x2e]
533+
534+
ite eq
535+
vcvtteq.f16.f32 s0, s1
536+
vcvttne.f16.f32 s0, s1
537+
# CHECK: ite eq @ encoding: [0x0c,0xbf]
538+
# CHECK: vcvtteq.f16.f32 s0, s1 @ encoding: [0xb3,0xee,0xe0,0x0a]
539+
# CHECK-NOFP-NOT: vcvtteq.f16.f32 s0, s1 @ encoding: [0xb3,0xee,0xe0,0x0a]
540+
# CHECK: vcvttne.f16.f32 s0, s1 @ encoding: [0xb3,0xee,0xe0,0x0a]
541+
# CHECK-NOFP-NOT: vcvttne.f16.f32 s0, s1 @ encoding: [0xb3,0xee,0xe0,0x0a]

‎llvm/test/MC/Disassembler/ARM/mve-qdest-qsrc.txt

Lines changed: 391 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,391 @@
1+
# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
2+
# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
3+
# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
4+
5+
# CHECK: vqdmladhx.s8 q1, q6, q6 @ encoding: [0x0c,0xee,0x0c,0x3e]
6+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
7+
[0x0c,0xee,0x0c,0x3e]
8+
9+
# CHECK: vqdmladhx.s16 q0, q1, q4 @ encoding: [0x12,0xee,0x08,0x1e]
10+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
11+
[0x12,0xee,0x08,0x1e]
12+
13+
# CHECK: vqdmladhx.s32 q0, q3, q7 @ encoding: [0x26,0xee,0x0e,0x1e]
14+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
15+
[0x26,0xee,0x0e,0x1e]
16+
17+
# CHECK: vqdmladh.s8 q0, q1, q1 @ encoding: [0x02,0xee,0x02,0x0e]
18+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
19+
[0x02,0xee,0x02,0x0e]
20+
21+
# CHECK: vqdmladh.s16 q0, q2, q2 @ encoding: [0x14,0xee,0x04,0x0e]
22+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
23+
[0x14,0xee,0x04,0x0e]
24+
25+
# CHECK: vqdmladh.s32 q1, q5, q7 @ encoding: [0x2a,0xee,0x0e,0x2e]
26+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
27+
[0x2a,0xee,0x0e,0x2e]
28+
29+
# CHECK: vqrdmladhx.s8 q0, q7, q0 @ encoding: [0x0e,0xee,0x01,0x1e]
30+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
31+
[0x0e,0xee,0x01,0x1e]
32+
33+
# CHECK: vqrdmladhx.s16 q0, q0, q1 @ encoding: [0x10,0xee,0x03,0x1e]
34+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
35+
[0x10,0xee,0x03,0x1e]
36+
37+
# CHECK: vqrdmladhx.s32 q1, q0, q4 @ encoding: [0x20,0xee,0x09,0x3e]
38+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
39+
[0x20,0xee,0x09,0x3e]
40+
41+
# CHECK: vqrdmladh.s8 q0, q6, q2 @ encoding: [0x0c,0xee,0x05,0x0e]
42+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
43+
[0x0c,0xee,0x05,0x0e]
44+
45+
# CHECK: vqrdmladh.s16 q1, q5, q4 @ encoding: [0x1a,0xee,0x09,0x2e]
46+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
47+
[0x1a,0xee,0x09,0x2e]
48+
49+
# CHECK: vqrdmladh.s32 q0, q2, q2 @ encoding: [0x24,0xee,0x05,0x0e]
50+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
51+
[0x24,0xee,0x05,0x0e]
52+
53+
# CHECK: vqdmlsdhx.s8 q1, q4, q7 @ encoding: [0x08,0xfe,0x0e,0x3e]
54+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
55+
[0x08,0xfe,0x0e,0x3e]
56+
57+
# CHECK: vqdmlsdhx.s16 q0, q2, q5 @ encoding: [0x14,0xfe,0x0a,0x1e]
58+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
59+
[0x14,0xfe,0x0a,0x1e]
60+
61+
# CHECK: vqdmlsdhx.s32 q3, q4, q6 @ encoding: [0x28,0xfe,0x0c,0x7e]
62+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
63+
[0x28,0xfe,0x0c,0x7e]
64+
65+
# CHECK: vqdmlsdh.s8 q0, q3, q6 @ encoding: [0x06,0xfe,0x0c,0x0e]
66+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
67+
[0x06,0xfe,0x0c,0x0e]
68+
69+
# CHECK: vqdmlsdh.s16 q0, q4, q1 @ encoding: [0x18,0xfe,0x02,0x0e]
70+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
71+
[0x18,0xfe,0x02,0x0e]
72+
73+
# CHECK: vqdmlsdh.s32 q2, q5, q0 @ encoding: [0x2a,0xfe,0x00,0x4e]
74+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
75+
[0x2a,0xfe,0x00,0x4e]
76+
77+
# CHECK: vqrdmlsdhx.s8 q0, q3, q1 @ encoding: [0x06,0xfe,0x03,0x1e]
78+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
79+
[0x06,0xfe,0x03,0x1e]
80+
81+
# CHECK: vqrdmlsdhx.s16 q0, q1, q4 @ encoding: [0x12,0xfe,0x09,0x1e]
82+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
83+
[0x12,0xfe,0x09,0x1e]
84+
85+
# CHECK: vqrdmlsdhx.s32 q1, q6, q3 @ encoding: [0x2c,0xfe,0x07,0x3e]
86+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
87+
[0x2c,0xfe,0x07,0x3e]
88+
89+
# CHECK: vqrdmlsdh.s8 q3, q3, q0 @ encoding: [0x06,0xfe,0x01,0x6e]
90+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
91+
[0x06,0xfe,0x01,0x6e]
92+
93+
# CHECK: vqrdmlsdh.s16 q0, q7, q4 @ encoding: [0x1e,0xfe,0x09,0x0e]
94+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
95+
[0x1e,0xfe,0x09,0x0e]
96+
97+
# CHECK: vqrdmlsdh.s32 q0, q6, q7 @ encoding: [0x2c,0xfe,0x0f,0x0e]
98+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
99+
[0x2c,0xfe,0x0f,0x0e]
100+
101+
# CHECK: vcmul.f16 q6, q2, q5, #0 @ encoding: [0x34,0xee,0x0a,0xce]
102+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
103+
[0x34,0xee,0x0a,0xce]
104+
105+
# CHECK: vcmul.f16 q1, q0, q5, #90 @ encoding: [0x30,0xee,0x0b,0x2e]
106+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
107+
[0x30,0xee,0x0b,0x2e]
108+
109+
# CHECK: vcmul.f16 q1, q0, q5, #180 @ encoding: [0x30,0xee,0x0a,0x3e]
110+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
111+
[0x30,0xee,0x0a,0x3e]
112+
113+
# CHECK: vcmul.f16 q1, q0, q5, #270 @ encoding: [0x30,0xee,0x0b,0x3e]
114+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
115+
[0x30,0xee,0x0b,0x3e]
116+
117+
# CHECK: vcmul.f32 q1, q7, q5, #0 @ encoding: [0x3e,0xfe,0x0a,0x2e]
118+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
119+
[0x3e,0xfe,0x0a,0x2e]
120+
121+
# CHECK: vcmul.f32 q3, q4, q2, #90 @ encoding: [0x38,0xfe,0x05,0x6e]
122+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
123+
[0x38,0xfe,0x05,0x6e]
124+
125+
# CHECK: vcmul.f32 q5, q1, q3, #180 @ encoding: [0x32,0xfe,0x06,0xbe]
126+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
127+
[0x32,0xfe,0x06,0xbe]
128+
129+
# CHECK: vcmul.f32 q0, q7, q4, #270 @ encoding: [0x3e,0xfe,0x09,0x1e]
130+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
131+
[0x3e,0xfe,0x09,0x1e]
132+
133+
# CHECK: vmullb.s8 q2, q6, q0 @ encoding: [0x0d,0xee,0x00,0x4e]
134+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
135+
[0x0d,0xee,0x00,0x4e]
136+
137+
# CHECK: vmullb.s16 q3, q4, q3 @ encoding: [0x19,0xee,0x06,0x6e]
138+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
139+
[0x19,0xee,0x06,0x6e]
140+
141+
# CHECK: vmullb.s32 q3, q5, q6 @ encoding: [0x2b,0xee,0x0c,0x6e]
142+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
143+
[0x2b,0xee,0x0c,0x6e]
144+
145+
# CHECK: vmullt.s8 q0, q6, q2 @ encoding: [0x0d,0xee,0x04,0x1e]
146+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
147+
[0x0d,0xee,0x04,0x1e]
148+
149+
# CHECK: vmullt.s16 q0, q0, q2 @ encoding: [0x11,0xee,0x04,0x1e]
150+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
151+
[0x11,0xee,0x04,0x1e]
152+
153+
# CHECK: vmullt.s32 q2, q4, q4 @ encoding: [0x29,0xee,0x08,0x5e]
154+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
155+
[0x29,0xee,0x08,0x5e]
156+
157+
# CHECK: vmullb.p8 q2, q3, q7 @ encoding: [0x37,0xee,0x0e,0x4e]
158+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
159+
[0x37,0xee,0x0e,0x4e]
160+
161+
# CHECK: vmullb.p16 q0, q1, q3 @ encoding: [0x33,0xfe,0x06,0x0e]
162+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
163+
[0x33,0xfe,0x06,0x0e]
164+
165+
# CHECK: vmullt.p8 q1, q1, q7 @ encoding: [0x33,0xee,0x0e,0x3e]
166+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
167+
[0x33,0xee,0x0e,0x3e]
168+
169+
# CHECK: vmullt.p16 q0, q7, q7 @ encoding: [0x3f,0xfe,0x0e,0x1e]
170+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
171+
[0x3f,0xfe,0x0e,0x1e]
172+
173+
# CHECK: vmulh.s8 q0, q4, q5 @ encoding: [0x09,0xee,0x0b,0x0e]
174+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
175+
[0x09,0xee,0x0b,0x0e]
176+
177+
# CHECK: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
178+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
179+
[0x1f,0xee,0x09,0x0e]
180+
181+
# CHECK: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
182+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
183+
[0x2f,0xee,0x09,0x0e]
184+
185+
# CHECK: vmulh.u8 q3, q5, q2 @ encoding: [0x0b,0xfe,0x05,0x6e]
186+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
187+
[0x0b,0xfe,0x05,0x6e]
188+
189+
# CHECK: vmulh.u16 q2, q7, q4 @ encoding: [0x1f,0xfe,0x09,0x4e]
190+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
191+
[0x1f,0xfe,0x09,0x4e]
192+
193+
# CHECK: vmulh.u32 q1, q3, q2 @ encoding: [0x27,0xfe,0x05,0x2e]
194+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
195+
[0x27,0xfe,0x05,0x2e]
196+
197+
# CHECK: vrmulh.s8 q1, q1, q2 @ encoding: [0x03,0xee,0x05,0x3e]
198+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
199+
[0x03,0xee,0x05,0x3e]
200+
201+
# CHECK: vrmulh.s16 q1, q1, q2 @ encoding: [0x13,0xee,0x05,0x3e]
202+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
203+
[0x13,0xee,0x05,0x3e]
204+
205+
# CHECK: vrmulh.s32 q3, q1, q0 @ encoding: [0x23,0xee,0x01,0x7e]
206+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
207+
[0x23,0xee,0x01,0x7e]
208+
209+
# CHECK: vrmulh.u8 q1, q6, q0 @ encoding: [0x0d,0xfe,0x01,0x3e]
210+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
211+
[0x0d,0xfe,0x01,0x3e]
212+
213+
# CHECK: vrmulh.u16 q4, q3, q6 @ encoding: [0x17,0xfe,0x0d,0x9e]
214+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
215+
[0x17,0xfe,0x0d,0x9e]
216+
217+
# CHECK: vrmulh.u32 q1, q2, q2 @ encoding: [0x25,0xfe,0x05,0x3e]
218+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
219+
[0x25,0xfe,0x05,0x3e]
220+
221+
# CHECK: vqmovnb.s16 q0, q1 @ encoding: [0x33,0xee,0x03,0x0e]
222+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
223+
[0x33,0xee,0x03,0x0e]
224+
225+
# CHECK: vqmovnt.s16 q2, q0 @ encoding: [0x33,0xee,0x01,0x5e]
226+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
227+
[0x33,0xee,0x01,0x5e]
228+
229+
# CHECK: vqmovnb.s32 q0, q5 @ encoding: [0x37,0xee,0x0b,0x0e]
230+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
231+
[0x37,0xee,0x0b,0x0e]
232+
233+
# CHECK: vqmovnt.s32 q0, q1 @ encoding: [0x37,0xee,0x03,0x1e]
234+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
235+
[0x37,0xee,0x03,0x1e]
236+
237+
# CHECK: vqmovnb.u16 q0, q4 @ encoding: [0x33,0xfe,0x09,0x0e]
238+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
239+
[0x33,0xfe,0x09,0x0e]
240+
241+
# CHECK: vqmovnt.u16 q0, q7 @ encoding: [0x33,0xfe,0x0f,0x1e]
242+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
243+
[0x33,0xfe,0x0f,0x1e]
244+
245+
# CHECK: vqmovnb.u32 q0, q4 @ encoding: [0x37,0xfe,0x09,0x0e]
246+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
247+
[0x37,0xfe,0x09,0x0e]
248+
249+
# CHECK: vqmovnt.u32 q0, q2 @ encoding: [0x37,0xfe,0x05,0x1e]
250+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
251+
[0x37,0xfe,0x05,0x1e]
252+
253+
# CHECK: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
254+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
255+
[0x3f,0xee,0x09,0x2e]
256+
257+
# CHECK: vcvtt.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x3e]
258+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
259+
[0x3f,0xee,0x09,0x3e]
260+
261+
# CHECK: vcvtb.f32.f16 q0, q3 @ encoding: [0x3f,0xfe,0x07,0x0e]
262+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
263+
[0x3f,0xfe,0x07,0x0e]
264+
265+
# CHECK: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
266+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
267+
[0x3f,0xfe,0x03,0x1e]
268+
269+
# CHECK: vcvtb.f16.f32 q1, q4 @ encoding: [0x3f,0xee,0x09,0x2e]
270+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
271+
[0x3f,0xee,0x09,0x2e]
272+
273+
# CHECK: vcvtt.f32.f16 q0, q1 @ encoding: [0x3f,0xfe,0x03,0x1e]
274+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
275+
[0x3f,0xfe,0x03,0x1e]
276+
277+
# CHECK: vcvtt.f64.f16 d0, s0 @ encoding: [0xb2,0xee,0xc0,0x0b]
278+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
279+
[0xb2,0xee,0xc0,0x0b]
280+
281+
# CHECK: vcvtt.f16.f64 s1, d2 @ encoding: [0xf3,0xee,0xc2,0x0b]
282+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
283+
[0xf3,0xee,0xc2,0x0b]
284+
285+
# CHECK: vqmovunb.s16 q0, q3 @ encoding: [0x31,0xee,0x87,0x0e]
286+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
287+
[0x31,0xee,0x87,0x0e]
288+
289+
# CHECK: vqmovunt.s16 q4, q1 @ encoding: [0x31,0xee,0x83,0x9e]
290+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
291+
[0x31,0xee,0x83,0x9e]
292+
293+
# CHECK: vqmovunb.s32 q1, q7 @ encoding: [0x35,0xee,0x8f,0x2e]
294+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
295+
[0x35,0xee,0x8f,0x2e]
296+
297+
# CHECK: vqmovunt.s32 q0, q2 @ encoding: [0x35,0xee,0x85,0x1e]
298+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
299+
[0x35,0xee,0x85,0x1e]
300+
301+
# CHECK: vmovnb.i16 q1, q5 @ encoding: [0x31,0xfe,0x8b,0x2e]
302+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
303+
[0x31,0xfe,0x8b,0x2e]
304+
305+
# CHECK: vmovnt.i16 q0, q0 @ encoding: [0x31,0xfe,0x81,0x1e]
306+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
307+
[0x31,0xfe,0x81,0x1e]
308+
309+
# CHECK: vmovnb.i32 q1, q0 @ encoding: [0x35,0xfe,0x81,0x2e]
310+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
311+
[0x35,0xfe,0x81,0x2e]
312+
313+
# CHECK: vmovnt.i32 q3, q3 @ encoding: [0x35,0xfe,0x87,0x7e]
314+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
315+
[0x35,0xfe,0x87,0x7e]
316+
317+
# CHECK: vhcadd.s8 q3, q7, q5, #90 @ encoding: [0x0e,0xee,0x0a,0x6f]
318+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
319+
[0x0e,0xee,0x0a,0x6f]
320+
321+
# CHECK: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
322+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
323+
[0x10,0xee,0x0c,0x0f]
324+
325+
# CHECK: vhcadd.s16 q0, q0, q6, #90 @ encoding: [0x10,0xee,0x0c,0x0f]
326+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
327+
[0x10,0xee,0x0c,0x0f]
328+
329+
# CHECK: vhcadd.s16 q3, q1, q0, #270 @ encoding: [0x12,0xee,0x00,0x7f]
330+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
331+
[0x12,0xee,0x00,0x7f]
332+
333+
# CHECK: vhcadd.s32 q3, q4, q5, #90 @ encoding: [0x28,0xee,0x0a,0x6f]
334+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
335+
[0x28,0xee,0x0a,0x6f]
336+
337+
# CHECK: vhcadd.s32 q6, q7, q2, #270 @ encoding: [0x2e,0xee,0x04,0xdf]
338+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
339+
[0x2e,0xee,0x04,0xdf]
340+
341+
# CHECK: vadc.i32 q1, q0, q2 @ encoding: [0x30,0xee,0x04,0x2f]
342+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
343+
[0x30,0xee,0x04,0x2f]
344+
345+
# CHECK: vadci.i32 q0, q1, q1 @ encoding: [0x32,0xee,0x02,0x1f]
346+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
347+
[0x32,0xee,0x02,0x1f]
348+
349+
# CHECK: vcadd.i8 q1, q0, q2, #90 @ encoding: [0x00,0xfe,0x04,0x2f]
350+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
351+
[0x00,0xfe,0x04,0x2f]
352+
353+
# CHECK: vcadd.i16 q0, q2, q3, #90 @ encoding: [0x14,0xfe,0x06,0x0f]
354+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
355+
[0x14,0xfe,0x06,0x0f]
356+
357+
# CHECK: vcadd.i16 q0, q5, q5, #270 @ encoding: [0x1a,0xfe,0x0a,0x1f]
358+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
359+
[0x1a,0xfe,0x0a,0x1f]
360+
361+
# CHECK: vcadd.i32 q4, q2, q5, #90 @ encoding: [0x24,0xfe,0x0a,0x8f]
362+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
363+
[0x24,0xfe,0x0a,0x8f]
364+
365+
# CHECK: vcadd.i32 q5, q5, q0, #270 @ encoding: [0x2a,0xfe,0x00,0xbf]
366+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
367+
[0x2a,0xfe,0x00,0xbf]
368+
369+
# CHECK: vsbc.i32 q3, q1, q1 @ encoding: [0x32,0xfe,0x02,0x6f]
370+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
371+
[0x32,0xfe,0x02,0x6f]
372+
373+
# CHECK: vsbci.i32 q2, q6, q2 @ encoding: [0x3c,0xfe,0x04,0x5f]
374+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
375+
[0x3c,0xfe,0x04,0x5f]
376+
377+
# CHECK: vqdmullb.s16 q0, q4, q5 @ encoding: [0x38,0xee,0x0b,0x0f]
378+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
379+
[0x38,0xee,0x0b,0x0f]
380+
381+
# CHECK: vqdmullt.s16 q0, q6, q5 @ encoding: [0x3c,0xee,0x0b,0x1f]
382+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
383+
[0x3c,0xee,0x0b,0x1f]
384+
385+
# CHECK: vqdmullb.s32 q0, q3, q7 @ encoding: [0x36,0xfe,0x0f,0x0f]
386+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
387+
[0x36,0xfe,0x0f,0x0f]
388+
389+
# CHECK: vqdmullt.s32 q0, q7, q5 @ encoding: [0x3e,0xfe,0x0b,0x1f]
390+
# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
391+
[0x3e,0xfe,0x0b,0x1f]

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