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sdesmalen-armsdesmalen-arm
committedJun 13, 2019
Improve reduction intrinsics by overloading result value.
This patch uses the mechanism from D62995 to strengthen the definitions of the reduction intrinsics by letting the scalar result/accumulator type be overloaded from the vector element type. For example: ; The LLVM LangRef specifies that the scalar result must equal the ; vector element type, but this is not checked/enforced by LLVM. declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a) This patch changes that into: declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a) Which has the type-constraint more explicit and causes LLVM to check the result type with the vector element type. Reviewers: RKSimon, arsenm, rnk, greened, aemerson Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D62996 llvm-svn: 363240
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llvmorg-21-initllvmorg-9.0.0-rc1
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‎llvm/docs/LangRef.rst

+15-15
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@@ -13719,8 +13719,8 @@ Syntax:
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::
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declare i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32> %a)
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declare i64 @llvm.experimental.vector.reduce.add.i64.v2i64(<2 x i64> %a)
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declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %a)
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declare i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %a)
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"""""""""
@@ -13780,8 +13780,8 @@ Syntax:
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declare i32 @llvm.experimental.vector.reduce.mul.i32.v4i32(<4 x i32> %a)
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declare i64 @llvm.experimental.vector.reduce.mul.i64.v2i64(<2 x i64> %a)
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declare i32 @llvm.experimental.vector.reduce.mul.v4i32(<4 x i32> %a)
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declare i64 @llvm.experimental.vector.reduce.mul.v2i64(<2 x i64> %a)
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@@ -13840,7 +13840,7 @@ Syntax:
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declare i32 @llvm.experimental.vector.reduce.and.i32.v4i32(<4 x i32> %a)
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declare i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32> %a)
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@@ -13861,7 +13861,7 @@ Syntax:
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declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a)
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declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a)
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declare i32 @llvm.experimental.vector.reduce.xor.i32.v4i32(<4 x i32> %a)
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declare i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> %a)
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@@ -13903,7 +13903,7 @@ Syntax:
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declare i32 @llvm.experimental.vector.reduce.smax.i32.v4i32(<4 x i32> %a)
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declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %a)
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declare i32 @llvm.experimental.vector.reduce.smin.i32.v4i32(<4 x i32> %a)
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declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %a)
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declare i32 @llvm.experimental.vector.reduce.umax.i32.v4i32(<4 x i32> %a)
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declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %a)
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declare i32 @llvm.experimental.vector.reduce.umin.i32.v4i32(<4 x i32> %a)
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declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %a)
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declare float @llvm.experimental.vector.reduce.fmax.f32.v4f32(<4 x float> %a)
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declare double @llvm.experimental.vector.reduce.fmax.f64.v2f64(<2 x double> %a)
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declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %a)
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declare double @llvm.experimental.vector.reduce.fmax.v2f64(<2 x double> %a)
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declare float @llvm.experimental.vector.reduce.fmin.f32.v4f32(<4 x float> %a)
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declare double @llvm.experimental.vector.reduce.fmin.f64.v2f64(<2 x double> %a)
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declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %a)
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declare double @llvm.experimental.vector.reduce.fmin.v2f64(<2 x double> %a)
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"""""""""

‎llvm/include/llvm/IR/Intrinsics.h

+5-3
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@@ -99,7 +99,8 @@ namespace Intrinsic {
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Void, VarArg, MMX, Token, Metadata, Half, Float, Double, Quad,
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Integer, Vector, Pointer, Struct,
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Argument, ExtendArgument, TruncArgument, HalfVecArgument,
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SameVecWidthArgument, PtrToArgument, PtrToElt, VecOfAnyPtrsToElt
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SameVecWidthArgument, PtrToArgument, PtrToElt, VecOfAnyPtrsToElt,
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VecElementArgument
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} Kind;
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union {
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assert(Kind == Argument || Kind == ExtendArgument ||
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Kind == TruncArgument || Kind == HalfVecArgument ||
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Kind == SameVecWidthArgument || Kind == PtrToArgument ||
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Kind == PtrToElt);
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Kind == PtrToElt || Kind == VecElementArgument);
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return Argument_Info >> 3;
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}
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ArgKind getArgumentKind() const {
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assert(Kind == Argument || Kind == ExtendArgument ||
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Kind == TruncArgument || Kind == HalfVecArgument ||
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Kind == SameVecWidthArgument || Kind == PtrToArgument);
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Kind == SameVecWidthArgument || Kind == PtrToArgument ||
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Kind == VecElementArgument);
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return (ArgKind)(Argument_Info & 7);
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}
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