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Petar AvramovicPetar Avramovic
Petar Avramovic
authored and
Petar Avramovic
committedJun 6, 2019
[MIPS GlobalISel] Select sqrt
Select G_FSQRT for MIPS32. Differential Revision: https://reviews.llvm.org/D62905 llvm-svn: 362692
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+219
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6 files changed

+219
-2
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‎llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
9494
getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({s32, s64});
9696

97-
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS})
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getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT})
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.legalFor({s32, s64});
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100100
getActionDefinitionsBuilder(G_FCMP)

‎llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -134,7 +134,8 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
134134
case G_FSUB:
135135
case G_FMUL:
136136
case G_FDIV:
137-
case G_FABS: {
137+
case G_FABS:
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case G_FSQRT:{
138139
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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assert((Size == 32 || Size == 64) && "Unsupported floating point size");
140141
OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]

‎llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt.mir

+65
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@@ -0,0 +1,65 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
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--- |
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define void @sqrt_f32() {entry: ret void}
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define void @sqrt_f64() {entry: ret void}
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...
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---
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name: sqrt_f32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12
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; FP32-LABEL: name: sqrt_f32
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; FP32: liveins: $f12
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; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP32: [[FSQRT_S:%[0-9]+]]:fgr32 = FSQRT_S [[COPY]]
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; FP32: $f0 = COPY [[FSQRT_S]]
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: sqrt_f32
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; FP64: liveins: $f12
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; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP64: [[FSQRT_S:%[0-9]+]]:fgr32 = FSQRT_S [[COPY]]
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; FP64: $f0 = COPY [[FSQRT_S]]
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; FP64: RetRA implicit $f0
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%0:fprb(s32) = COPY $f12
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%1:fprb(s32) = G_FSQRT %0
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$f0 = COPY %1(s32)
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RetRA implicit $f0
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...
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---
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name: sqrt_f64
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6
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; FP32-LABEL: name: sqrt_f64
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; FP32: liveins: $d6
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; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
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; FP32: [[FSQRT_D32_:%[0-9]+]]:afgr64 = FSQRT_D32 [[COPY]]
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; FP32: $d0 = COPY [[FSQRT_D32_]]
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: sqrt_f64
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; FP64: liveins: $d6
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; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
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; FP64: [[FSQRT_D64_:%[0-9]+]]:fgr64 = FSQRT_D64 [[COPY]]
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; FP64: $d0 = COPY [[FSQRT_D64_]]
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; FP64: RetRA implicit $d0
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%0:fprb(s64) = COPY $d6
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%1:fprb(s64) = G_FSQRT %0
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$d0 = COPY %1(s64)
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RetRA implicit $d0
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...

‎llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt.mir

+61
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,61 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
3+
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
4+
--- |
5+
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define void @sqrt_f32() {entry: ret void}
7+
define void @sqrt_f64() {entry: ret void}
8+
9+
...
10+
---
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name: sqrt_f32
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alignment: 2
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tracksRegLiveness: true
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body: |
15+
bb.1.entry:
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liveins: $f12
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; FP32-LABEL: name: sqrt_f32
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; FP32: liveins: $f12
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP32: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]]
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; FP32: $f0 = COPY [[FSQRT]](s32)
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: sqrt_f32
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; FP64: liveins: $f12
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP64: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]]
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; FP64: $f0 = COPY [[FSQRT]](s32)
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; FP64: RetRA implicit $f0
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%0:_(s32) = COPY $f12
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%1:_(s32) = G_FSQRT %0
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$f0 = COPY %1(s32)
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RetRA implicit $f0
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...
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---
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name: sqrt_f64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6
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; FP32-LABEL: name: sqrt_f64
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; FP32: liveins: $d6
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; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
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; FP32: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]]
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; FP32: $d0 = COPY [[FSQRT]](s64)
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: sqrt_f64
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; FP64: liveins: $d6
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; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
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; FP64: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]]
54+
; FP64: $d0 = COPY [[FSQRT]](s64)
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; FP64: RetRA implicit $d0
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%0:_(s64) = COPY $d6
57+
%1:_(s64) = G_FSQRT %0
58+
$d0 = COPY %1(s64)
59+
RetRA implicit $d0
60+
61+
...

‎llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll

+27
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
3+
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
4+
5+
declare float @llvm.sqrt.f32(float)
6+
define float @sqrt_f32(float %a) {
7+
; MIPS32-LABEL: sqrt_f32:
8+
; MIPS32: # %bb.0: # %entry
9+
; MIPS32-NEXT: sqrt.s $f0, $f12
10+
; MIPS32-NEXT: jr $ra
11+
; MIPS32-NEXT: nop
12+
entry:
13+
%0 = call float @llvm.sqrt.f32(float %a)
14+
ret float %0
15+
}
16+
17+
declare double @llvm.sqrt.f64(double)
18+
define double @sqrt_f64(double %a) {
19+
; MIPS32-LABEL: sqrt_f64:
20+
; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: sqrt.d $f0, $f12
22+
; MIPS32-NEXT: jr $ra
23+
; MIPS32-NEXT: nop
24+
entry:
25+
%0 = call double @llvm.sqrt.f64(double %a)
26+
ret double %0
27+
}

‎llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir

+63
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,63 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
3+
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
4+
--- |
5+
6+
define void @sqrt_f32() {entry: ret void}
7+
define void @sqrt_f64() {entry: ret void}
8+
9+
...
10+
---
11+
name: sqrt_f32
12+
alignment: 2
13+
legalized: true
14+
tracksRegLiveness: true
15+
body: |
16+
bb.1.entry:
17+
liveins: $f12
18+
19+
; FP32-LABEL: name: sqrt_f32
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; FP32: liveins: $f12
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; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
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; FP32: [[FSQRT:%[0-9]+]]:fprb(s32) = G_FSQRT [[COPY]]
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; FP32: $f0 = COPY [[FSQRT]](s32)
24+
; FP32: RetRA implicit $f0
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; FP64-LABEL: name: sqrt_f32
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; FP64: liveins: $f12
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; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
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; FP64: [[FSQRT:%[0-9]+]]:fprb(s32) = G_FSQRT [[COPY]]
29+
; FP64: $f0 = COPY [[FSQRT]](s32)
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; FP64: RetRA implicit $f0
31+
%0:_(s32) = COPY $f12
32+
%1:_(s32) = G_FSQRT %0
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$f0 = COPY %1(s32)
34+
RetRA implicit $f0
35+
36+
...
37+
---
38+
name: sqrt_f64
39+
alignment: 2
40+
legalized: true
41+
tracksRegLiveness: true
42+
body: |
43+
bb.1.entry:
44+
liveins: $d6
45+
46+
; FP32-LABEL: name: sqrt_f64
47+
; FP32: liveins: $d6
48+
; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
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; FP32: [[FSQRT:%[0-9]+]]:fprb(s64) = G_FSQRT [[COPY]]
50+
; FP32: $d0 = COPY [[FSQRT]](s64)
51+
; FP32: RetRA implicit $d0
52+
; FP64-LABEL: name: sqrt_f64
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; FP64: liveins: $d6
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; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
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; FP64: [[FSQRT:%[0-9]+]]:fprb(s64) = G_FSQRT [[COPY]]
56+
; FP64: $d0 = COPY [[FSQRT]](s64)
57+
; FP64: RetRA implicit $d0
58+
%0:_(s64) = COPY $d6
59+
%1:_(s64) = G_FSQRT %0
60+
$d0 = COPY %1(s64)
61+
RetRA implicit $d0
62+
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...

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