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committedMay 1, 2019
[AMDGPU] gfx1010 GCNRegBankReassign pass
Reassign registers to reduce register bank conflicts. Differential Revision: https://reviews.llvm.org/D61344 llvm-svn: 359704
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‎llvm/lib/Target/AMDGPU/AMDGPU.h

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@@ -221,6 +221,9 @@ ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
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void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
222222
extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
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224+
void initializeGCNRegBankReassignPass(PassRegistry &);
225+
extern char &GCNRegBankReassignID;
226+
224227
void initializeGCNNSAReassignPass(PassRegistry &);
225228
extern char &GCNNSAReassignID;
226229

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

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@@ -234,6 +234,7 @@ extern "C" void LLVMInitializeAMDGPUTarget() {
234234
initializeAMDGPUUseNativeCallsPass(*PR);
235235
initializeAMDGPUSimplifyLibCallsPass(*PR);
236236
initializeAMDGPUInlinerPass(*PR);
237+
initializeGCNRegBankReassignPass(*PR);
237238
initializeGCNNSAReassignPass(*PR);
238239
}
239240

@@ -937,6 +938,7 @@ void GCNPassConfig::addOptimizedRegAlloc() {
937938
bool GCNPassConfig::addPreRewrite() {
938939
if (EnableRegReassign) {
939940
addPass(&GCNNSAReassignID);
941+
addPass(&GCNRegBankReassignID);
940942
}
941943
return true;
942944
}

‎llvm/lib/Target/AMDGPU/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -116,6 +116,7 @@ add_llvm_target(AMDGPUCodeGen
116116
SIShrinkInstructions.cpp
117117
SIWholeQuadMode.cpp
118118
GCNILPSched.cpp
119+
GCNRegBankReassign.cpp
119120
GCNNSAReassign.cpp
120121
GCNDPPCombine.cpp
121122
SIModeRegister.cpp

‎llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp

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@@ -0,0 +1,336 @@
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass greedy,amdgpu-regbanks-reassign,virtregrewriter -o - %s | FileCheck -check-prefix=GCN %s
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3+
# GCN-LABEL: v1_vs_v5{{$}}
4+
# GCN: V_AND_B32_e32 killed $vgpr3, killed $vgpr1,
5+
---
6+
name: v1_vs_v5
7+
tracksRegLiveness: true
8+
registers:
9+
- { id: 0, class: vgpr_32, preferred-register: '$vgpr1' }
10+
- { id: 1, class: vgpr_32, preferred-register: '$vgpr5' }
11+
- { id: 2, class: vgpr_32 }
12+
body: |
13+
bb.0:
14+
%0 = IMPLICIT_DEF
15+
%1 = IMPLICIT_DEF
16+
%2 = V_AND_B32_e32 %1, %0, implicit $exec
17+
S_ENDPGM 0
18+
...
19+
20+
# GCN-LABEL: v0_1_vs_v4{{$}}
21+
# GCN: GLOBAL_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr3,
22+
---
23+
name: v0_1_vs_v4
24+
tracksRegLiveness: true
25+
registers:
26+
- { id: 0, class: vgpr_32, preferred-register: '$vgpr4' }
27+
- { id: 1, class: vreg_64, preferred-register: '$vgpr0_vgpr1' }
28+
body: |
29+
bb.0:
30+
%0 = IMPLICIT_DEF
31+
%1 = IMPLICIT_DEF
32+
GLOBAL_STORE_DWORD %1, %0, 0, 0, 0, 0, implicit $exec
33+
S_ENDPGM 0
34+
...
35+
36+
# GCN-LABEL: v1_2_vs_v4_5{{$}}
37+
# GCN: GLOBAL_STORE_DWORDX2 killed renamable $vgpr2_vgpr3, killed renamable $vgpr4_vgpr5,
38+
---
39+
name: v1_2_vs_v4_5
40+
tracksRegLiveness: true
41+
registers:
42+
- { id: 0, class: vreg_64, preferred-register: '$vgpr4_vgpr5' }
43+
- { id: 1, class: vreg_64, preferred-register: '$vgpr1_vgpr2' }
44+
body: |
45+
bb.0:
46+
%0 = IMPLICIT_DEF
47+
%1 = IMPLICIT_DEF
48+
GLOBAL_STORE_DWORDX2 %1, %0, 0, 0, 0, 0, implicit $exec
49+
S_ENDPGM 0
50+
...
51+
52+
# GCN-LABEL: s0_vs_s16{{$}}
53+
# GCN: S_AND_B32 killed renamable $sgpr14, $sgpr0,
54+
---
55+
name: s0_vs_s16
56+
tracksRegLiveness: true
57+
registers:
58+
- { id: 0, class: sgpr_32, preferred-register: '$sgpr16' }
59+
- { id: 1, class: sgpr_32 }
60+
body: |
61+
bb.0:
62+
%0 = IMPLICIT_DEF
63+
$sgpr0 = IMPLICIT_DEF
64+
%1 = S_AND_B32 %0, $sgpr0, implicit-def $scc
65+
S_ENDPGM 0
66+
...
67+
68+
# GCN-LABEL: s1_vs_s16{{$}}
69+
# GCN: S_AND_B32 killed renamable $sgpr14, $sgpr1,
70+
---
71+
name: s1_vs_s16
72+
tracksRegLiveness: true
73+
registers:
74+
- { id: 0, class: sgpr_32, preferred-register: '$sgpr16' }
75+
- { id: 1, class: sgpr_32 }
76+
body: |
77+
bb.0:
78+
%0 = IMPLICIT_DEF
79+
$sgpr1 = IMPLICIT_DEF
80+
%1 = S_AND_B32 %0, $sgpr1, implicit-def $scc
81+
S_ENDPGM 0
82+
...
83+
84+
# GCN-LABEL: s12_vs_null{{$}}
85+
# GCN: S_AND_B32 $sgpr_null, killed renamable $sgpr14,
86+
---
87+
name: s12_vs_null
88+
tracksRegLiveness: true
89+
registers:
90+
- { id: 0, class: sgpr_32, preferred-register: '$sgpr12' }
91+
- { id: 1, class: sgpr_32 }
92+
body: |
93+
bb.0:
94+
%0 = IMPLICIT_DEF
95+
%1 = S_AND_B32 $sgpr_null, %0, implicit-def $scc
96+
S_ENDPGM 0
97+
...
98+
99+
# GCN-LABEL: s13_vs_m0{{$}}
100+
# GCN: S_AND_B32 $m0, killed renamable $sgpr14,
101+
---
102+
name: s13_vs_m0
103+
tracksRegLiveness: true
104+
registers:
105+
- { id: 0, class: sgpr_32, preferred-register: '$sgpr13' }
106+
- { id: 1, class: sgpr_32 }
107+
body: |
108+
bb.0:
109+
%0 = IMPLICIT_DEF
110+
%1 = S_AND_B32 $m0, %0, implicit-def $scc
111+
S_ENDPGM 0
112+
...
113+
114+
# GCN-LABEL: s12_13_vs_s28_s29{{$}}
115+
# GCN: S_AND_B64 $sgpr28_sgpr29, killed renamable $sgpr14_sgpr15,
116+
---
117+
name: s12_13_vs_s28_s29
118+
tracksRegLiveness: true
119+
registers:
120+
- { id: 0, class: sreg_64, preferred-register: '$sgpr12_sgpr13' }
121+
- { id: 1, class: sreg_64 }
122+
body: |
123+
bb.0:
124+
%0 = IMPLICIT_DEF
125+
$sgpr28_sgpr29 = IMPLICIT_DEF
126+
%1 = S_AND_B64 $sgpr28_sgpr29, %0, implicit-def $scc
127+
S_ENDPGM 0
128+
...
129+
130+
# GCN-LABEL: livein{{$}}
131+
# GCN: V_AND_B32_e32 killed $vgpr4, killed $vgpr0,
132+
---
133+
name: livein
134+
tracksRegLiveness: true
135+
registers:
136+
- { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
137+
- { id: 1, class: vgpr_32, preferred-register: '$vgpr4' }
138+
- { id: 2, class: vgpr_32 }
139+
liveins:
140+
- { reg: '$vgpr0', virtual-reg: '' }
141+
- { reg: '$vgpr4', virtual-reg: '' }
142+
body: |
143+
bb.0:
144+
liveins: $vgpr0, $vgpr4
145+
146+
%0 = COPY $vgpr0
147+
%1 = COPY $vgpr4
148+
%2 = V_AND_B32_e32 %1, %0, implicit $exec
149+
S_ENDPGM 0
150+
...
151+
152+
# GCN-LABEL: liveout{{$}}
153+
# GCN: V_AND_B32_e32 $vgpr4, $vgpr0,
154+
---
155+
name: liveout
156+
tracksRegLiveness: true
157+
registers:
158+
- { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
159+
- { id: 1, class: vgpr_32, preferred-register: '$vgpr4' }
160+
- { id: 2, class: vgpr_32 }
161+
body: |
162+
bb.0:
163+
%0 = IMPLICIT_DEF
164+
%1 = IMPLICIT_DEF
165+
%2 = V_AND_B32_e32 %1, %0, implicit $exec
166+
$vgpr0 = COPY %0
167+
$vgpr4 = COPY %1
168+
S_ENDPGM 0
169+
...
170+
171+
# GCN-LABEL: implicit{{$}}
172+
# GCN: V_MOV_B32_indirect undef $vgpr4, undef $vgpr0, implicit $exec, implicit-def dead renamable $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr4_vgpr5_vgpr6_vgpr7, implicit $m0
173+
---
174+
name: implicit
175+
tracksRegLiveness: true
176+
registers:
177+
- { id: 0, class: vreg_128 }
178+
- { id: 1, class: vreg_128, preferred-register: '$vgpr4_vgpr5_vgpr6_vgpr7' }
179+
body: |
180+
bb.0:
181+
%1 = IMPLICIT_DEF
182+
V_MOV_B32_indirect undef %1.sub0:vreg_128, undef $vgpr0, implicit $exec, implicit-def %0:vreg_128, implicit %1:vreg_128, implicit $m0
183+
S_ENDPGM 0
184+
...
185+
186+
# GCN-LABEL: occupancy_limit{{$}}
187+
# GCN: V_AND_B32_e32 $vgpr4, $vgpr0,
188+
---
189+
name: occupancy_limit
190+
tracksRegLiveness: true
191+
registers:
192+
- { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
193+
- { id: 1, class: vgpr_32, preferred-register: '$vgpr4' }
194+
- { id: 2, class: vgpr_32, preferred-register: '$vgpr1' }
195+
- { id: 3, class: vreg_64, preferred-register: '$vgpr2_vgpr3' }
196+
- { id: 4, class: vgpr_32, preferred-register: '$vgpr5' }
197+
- { id: 5, class: vreg_64, preferred-register: '$vgpr6_vgpr7' }
198+
- { id: 6, class: vreg_128, preferred-register: '$vgpr8_vgpr9_vgpr10_vgpr11' }
199+
- { id: 7, class: vreg_128, preferred-register: '$vgpr12_vgpr13_vgpr14_vgpr15' }
200+
- { id: 8, class: vreg_128, preferred-register: '$vgpr16_vgpr17_vgpr18_vgpr19' }
201+
- { id: 9, class: vreg_128, preferred-register: '$vgpr20_vgpr21_vgpr22_vgpr23' }
202+
body: |
203+
bb.0:
204+
%0 = IMPLICIT_DEF
205+
%1 = IMPLICIT_DEF
206+
%3 = IMPLICIT_DEF
207+
%4 = IMPLICIT_DEF
208+
%5 = IMPLICIT_DEF
209+
%6 = IMPLICIT_DEF
210+
%7 = IMPLICIT_DEF
211+
%8 = IMPLICIT_DEF
212+
%9 = IMPLICIT_DEF
213+
%2 = V_AND_B32_e32 %1, %0, implicit $exec
214+
GLOBAL_STORE_DWORD %3, %0, 0, 0, 0, 0, implicit $exec
215+
GLOBAL_STORE_DWORD %3, %1, 0, 0, 0, 0, implicit $exec
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GLOBAL_STORE_DWORD %3, %2, 0, 0, 0, 0, implicit $exec
217+
GLOBAL_STORE_DWORD %3, %4, 0, 0, 0, 0, implicit $exec
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GLOBAL_STORE_DWORDX2 %3, %5, 0, 0, 0, 0, implicit $exec
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GLOBAL_STORE_DWORDX4 %3, %6, 0, 0, 0, 0, implicit $exec
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GLOBAL_STORE_DWORDX4 %3, %7, 0, 0, 0, 0, implicit $exec
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GLOBAL_STORE_DWORDX4 %3, %8, 0, 0, 0, 0, implicit $exec
222+
GLOBAL_STORE_DWORDX4 %3, %9, 0, 0, 0, 0, implicit $exec
223+
S_ENDPGM 0
224+
...
225+
226+
# GCN-LABEL: csr{{$}}
227+
# GCN: V_AND_B32_e32 $vgpr4, $vgpr0,
228+
---
229+
name: csr
230+
tracksRegLiveness: true
231+
registers:
232+
- { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
233+
- { id: 1, class: vgpr_32, preferred-register: '$vgpr4' }
234+
- { id: 2, class: vgpr_32, preferred-register: '$vgpr1' }
235+
- { id: 3, class: vreg_64, preferred-register: '$vgpr2_vgpr3' }
236+
- { id: 4, class: vgpr_32, preferred-register: '$vgpr5' }
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- { id: 5, class: vreg_64, preferred-register: '$vgpr6_vgpr7' }
238+
- { id: 6, class: vreg_128, preferred-register: '$vgpr8_vgpr9_vgpr10_vgpr11' }
239+
- { id: 7, class: vreg_128, preferred-register: '$vgpr12_vgpr13_vgpr14_vgpr15' }
240+
- { id: 8, class: vreg_128, preferred-register: '$vgpr16_vgpr17_vgpr18_vgpr19' }
241+
- { id: 9, class: vreg_128, preferred-register: '$vgpr20_vgpr21_vgpr22_vgpr23' }
242+
- { id: 10, class: vreg_128, preferred-register: '$vgpr24_vgpr25_vgpr26_vgpr27' }
243+
- { id: 11, class: vreg_128, preferred-register: '$vgpr28_vgpr29_vgpr30_vgpr31' }
244+
- { id: 12, class: vgpr_32, preferred-register: '$vgpr33' }
245+
body: |
246+
bb.0:
247+
%0 = IMPLICIT_DEF
248+
%1 = IMPLICIT_DEF
249+
%3 = IMPLICIT_DEF
250+
%4 = IMPLICIT_DEF
251+
%5 = IMPLICIT_DEF
252+
%6 = IMPLICIT_DEF
253+
%7 = IMPLICIT_DEF
254+
%8 = IMPLICIT_DEF
255+
%9 = IMPLICIT_DEF
256+
%10 = IMPLICIT_DEF
257+
%11 = IMPLICIT_DEF
258+
%12 = IMPLICIT_DEF
259+
%2 = V_AND_B32_e32 %1, %0, implicit $exec
260+
GLOBAL_STORE_DWORD %3, %0, 0, 0, 0, 0, implicit $exec
261+
GLOBAL_STORE_DWORD %3, %1, 0, 0, 0, 0, implicit $exec
262+
GLOBAL_STORE_DWORD %3, %2, 0, 0, 0, 0, implicit $exec
263+
GLOBAL_STORE_DWORD %3, %4, 0, 0, 0, 0, implicit $exec
264+
GLOBAL_STORE_DWORDX2 %3, %5, 0, 0, 0, 0, implicit $exec
265+
GLOBAL_STORE_DWORDX4 %3, %6, 0, 0, 0, 0, implicit $exec
266+
GLOBAL_STORE_DWORDX4 %3, %7, 0, 0, 0, 0, implicit $exec
267+
GLOBAL_STORE_DWORDX4 %3, %8, 0, 0, 0, 0, implicit $exec
268+
GLOBAL_STORE_DWORDX4 %3, %9, 0, 0, 0, 0, implicit $exec
269+
GLOBAL_STORE_DWORDX4 %3, %10, 0, 0, 0, 0, implicit $exec
270+
GLOBAL_STORE_DWORDX4 %3, %11, 0, 0, 0, 0, implicit $exec
271+
GLOBAL_STORE_DWORD %3, %12, 0, 0, 0, 0, implicit $exec
272+
S_ENDPGM 0
273+
...
274+
275+
# Do not touch undefs
276+
# GCN-LABEL: s0_vs_s16_undef{{$}}
277+
# GCN: S_AND_B32 killed renamable $sgpr16, undef $sgpr0,
278+
---
279+
name: s0_vs_s16_undef
280+
tracksRegLiveness: true
281+
registers:
282+
- { id: 0, class: sgpr_32, preferred-register: '$sgpr16' }
283+
- { id: 1, class: sgpr_32 }
284+
body: |
285+
bb.0:
286+
%0 = IMPLICIT_DEF
287+
%1 = S_AND_B32 %0, undef $sgpr0, implicit-def $scc
288+
S_ENDPGM 0
289+
...
290+
291+
# GCN-LABEL: smem_bundle{{$}}
292+
# GCN: S_BUFFER_LOAD_DWORD_SGPR renamable $sgpr0_sgpr1_sgpr2_sgpr3, renamable $sgpr15, 0, 0
293+
# GCN: S_BUFFER_LOAD_DWORD_SGPR renamable $sgpr0_sgpr1_sgpr2_sgpr3, renamable $sgpr14, 0, 0
294+
---
295+
name: smem_bundle
296+
tracksRegLiveness: true
297+
registers:
298+
- { id: 0, class: sreg_128, preferred-register: '$sgpr0_sgpr1_sgpr2_sgpr3' }
299+
- { id: 1, class: sreg_32_xm0_xexec, preferred-register: '$sgpr16' }
300+
- { id: 2, class: sreg_32_xm0_xexec, preferred-register: '$sgpr17' }
301+
- { id: 3, class: sreg_32_xm0_xexec, preferred-register: '$sgpr4' }
302+
- { id: 4, class: sreg_32_xm0_xexec, preferred-register: '$sgpr5' }
303+
body: |
304+
bb.0:
305+
%0 = IMPLICIT_DEF
306+
%1 = IMPLICIT_DEF
307+
%2 = IMPLICIT_DEF
308+
early-clobber %3, early-clobber %4 = BUNDLE %0, %1, %2 {
309+
%3 = S_BUFFER_LOAD_DWORD_SGPR %0, %1, 0, 0
310+
%4 = S_BUFFER_LOAD_DWORD_SGPR %0, %2, 0, 0
311+
}
312+
S_ENDPGM 0
313+
...
314+
315+
# GCN-LABEL: vreg_512_subs{{$}}
316+
# don't care about the assignment: this used to trigger an infinite loop
317+
---
318+
name: vreg_512_subs
319+
tracksRegLiveness: true
320+
registers:
321+
- { id: 1, class: vreg_512, preferred-register: '$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15' }
322+
- { id: 2, class: vgpr_32, preferred-register: '$vgpr28' }
323+
body: |
324+
bb.0:
325+
%1 = IMPLICIT_DEF
326+
%2 = IMPLICIT_DEF
327+
DS_WRITE2_B32_gfx9 %2, %1.sub0, %1.sub1, 0, 1, 0, implicit $exec
328+
DS_WRITE2_B32_gfx9 %2, %1.sub2, %1.sub3, 2, 3, 0, implicit $exec
329+
DS_WRITE2_B32_gfx9 %2, %1.sub4, %1.sub5, 4, 5, 0, implicit $exec
330+
DS_WRITE2_B32_gfx9 %2, %1.sub6, %1.sub7, 6, 7, 0, implicit $exec
331+
DS_WRITE2_B32_gfx9 %2, %1.sub8, %1.sub9, 8, 9, 0, implicit $exec
332+
DS_WRITE2_B32_gfx9 %2, %1.sub10, %1.sub11, 10, 11, 0, implicit $exec
333+
DS_WRITE2_B32_gfx9 %2, %1.sub12, %1.sub13, 12, 13, 0, implicit $exec
334+
DS_WRITE2_B32_gfx9 %2, %1.sub14, %1.sub15, 14, 15, 0, implicit $exec
335+
S_ENDPGM 0
336+
...

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