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committedApr 16, 2019
[InstCombine] Prune fshl/fshr with masked operands
If a constant shift amount is used, then only some of the LHS/RHS operand bits are demanded and we may be able to simplify based on that. InstCombineSimplifyDemanded already had the necessary support for that, we just weren't calling it with fshl/fshr as root. In particular, this allows us to relax some masked funnel shifts into simple shifts, as shown in the tests. Patch by Shawn Landden. Differential Revision: https://reviews.llvm.org/D60660 llvm-svn: 358515
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+12
-12
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‎llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

+4
Original file line numberDiff line numberDiff line change
@@ -2085,6 +2085,10 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
20852085
ConstantExpr::getSub(WidthC, ShAmtC));
20862086
}
20872087

2088+
// Left or right might be masked.
2089+
if (SimplifyDemandedInstructionBits(*II))
2090+
return &CI;
2091+
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// The shift amount (operand 2) of a funnel shift is modulo the bitwidth,
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// so only the low bits of the shift amount are demanded if the bitwidth is
20902094
// a power-of-2.

‎llvm/test/Transforms/InstCombine/fsh.ll

+8-12
Original file line numberDiff line numberDiff line change
@@ -561,8 +561,7 @@ define i16 @fshr_bswap(i16 %x) {
561561

562562
define i32 @fshl_mask_args_same1(i32 %a) {
563563
; CHECK-LABEL: @fshl_mask_args_same1(
564-
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], -65536
565-
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 16)
564+
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[A:%.*]], 16
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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%tmp1 = and i32 %a, 4294901760 ; 0xffff0000
@@ -572,8 +571,8 @@ define i32 @fshl_mask_args_same1(i32 %a) {
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573572
define i32 @fshl_mask_args_same2(i32 %a) {
574573
; CHECK-LABEL: @fshl_mask_args_same2(
575-
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 255
576-
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 8)
574+
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[A:%.*]], 8
575+
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 65280
577576
; CHECK-NEXT: ret i32 [[TMP2]]
578577
;
579578
%tmp1 = and i32 %a, 255
@@ -583,8 +582,7 @@ define i32 @fshl_mask_args_same2(i32 %a) {
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584583
define i32 @fshl_mask_args_same3(i32 %a) {
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; CHECK-LABEL: @fshl_mask_args_same3(
586-
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A:%.*]], 255
587-
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP1]], i32 24)
585+
; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[A:%.*]], 24
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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%tmp1 = and i32 %a, 255
@@ -594,9 +592,8 @@ define i32 @fshl_mask_args_same3(i32 %a) {
594592

595593
define i32 @fshl_mask_args_different(i32 %a) {
596594
; CHECK-LABEL: @fshl_mask_args_different(
597-
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[A:%.*]], -65536
598-
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[A]], -16777216
599-
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP2]], i32 [[TMP1]], i32 17)
595+
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[A:%.*]], 15
596+
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP1]], 130560
600597
; CHECK-NEXT: ret i32 [[TMP3]]
601598
;
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%tmp2 = and i32 %a, 4294901760 ; 0xfffff00f
@@ -607,8 +604,7 @@ define i32 @fshl_mask_args_different(i32 %a) {
607604

608605
define <2 x i31> @fshr_mask_args_same_vector(<2 x i31> %a) {
609606
; CHECK-LABEL: @fshr_mask_args_same_vector(
610-
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i31> [[A:%.*]], <i31 1000, i31 1000>
611-
; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i31> @llvm.fshl.v2i31(<2 x i31> [[A]], <2 x i31> [[TMP1]], <2 x i31> <i31 10, i31 10>)
607+
; CHECK-NEXT: [[TMP3:%.*]] = shl <2 x i31> [[A:%.*]], <i31 10, i31 10>
612608
; CHECK-NEXT: ret <2 x i31> [[TMP3]]
613609
;
614610
%tmp1 = and <2 x i31> %a, <i31 1000, i31 1000>
@@ -620,7 +616,7 @@ define <2 x i31> @fshr_mask_args_same_vector(<2 x i31> %a) {
620616
define <2 x i32> @fshr_mask_args_same_vector2(<2 x i32> %a, <2 x i32> %b) {
621617
; CHECK-LABEL: @fshr_mask_args_same_vector2(
622618
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[A:%.*]], <i32 1000000, i32 100000>
623-
; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP1]], <2 x i32> <i32 29, i32 29>)
619+
; CHECK-NEXT: [[TMP3:%.*]] = lshr exact <2 x i32> [[TMP1]], <i32 3, i32 3>
624620
; CHECK-NEXT: ret <2 x i32> [[TMP3]]
625621
;
626622
%tmp1 = and <2 x i32> %a, <i32 1000000, i32 100000>

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