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davemgreendavemgreen
committedApr 10, 2019
Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg
Certain optimisations from ConstantHoisting and CGP rely on Selection DAG not seeing through to the constant in other blocks. Revert this patch while we come up with a better way to handle that. I will try to follow this up with some better tests. llvm-svn: 358113
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8 files changed

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‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 0 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,6 @@
3131
#include "llvm/CodeGen/MachineFrameInfo.h"
3232
#include "llvm/CodeGen/MachineFunction.h"
3333
#include "llvm/CodeGen/MachineMemOperand.h"
34-
#include "llvm/CodeGen/MachineRegisterInfo.h"
3534
#include "llvm/CodeGen/RuntimeLibcalls.h"
3635
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
3736
#include "llvm/CodeGen/SelectionDAGNodes.h"
@@ -3208,25 +3207,6 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
32083207
Known.One &= Known2.One;
32093208
break;
32103209
}
3211-
case ISD::CopyFromReg: {
3212-
auto R = cast<RegisterSDNode>(Op.getOperand(1));
3213-
const unsigned Reg = R->getReg();
3214-
3215-
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
3216-
if (!TRI->isVirtualRegister(Reg))
3217-
break;
3218-
3219-
const MachineRegisterInfo *MRI = &MF->getRegInfo();
3220-
if (!MRI->hasOneDef(Reg))
3221-
break;
3222-
3223-
const FunctionLoweringInfo::LiveOutInfo *LOI = FLI->GetLiveOutRegInfo(Reg);
3224-
if (!LOI || LOI->Known.getBitWidth() != BitWidth)
3225-
break;
3226-
3227-
Known = LOI->Known;
3228-
break;
3229-
}
32303210
case ISD::FrameIndex:
32313211
case ISD::TargetFrameIndex:
32323212
TLI->computeKnownBitsForFrameIndex(Op, Known, DemandedElts, *this, Depth);

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19595,10 +19595,10 @@ static SDValue LowerAndToBT(SDValue And, ISD::CondCode CC,
1959519595
DAG.MaskedValueIsZero(BitNo, APInt(BitNo.getValueSizeInBits(), 32)))
1959619596
Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
1959719597

19598-
// If the operand types disagree, extend or truncate the shift amount to match.
19599-
// Since BT ignores high bits (like shifts) we can use anyextend for the extension.
19598+
// If the operand types disagree, extend the shift amount to match. Since
19599+
// BT ignores high bits (like shifts) we can use anyextend.
1960019600
if (Src.getValueType() != BitNo.getValueType())
19601-
BitNo = DAG.getAnyExtOrTrunc(BitNo, dl, Src.getValueType());
19601+
BitNo = DAG.getNode(ISD::ANY_EXTEND, dl, Src.getValueType(), BitNo);
1960219602

1960319603
X86CC = DAG.getConstant(CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B,
1960419604
dl, MVT::i8);

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -110,8 +110,8 @@ main_body:
110110

111111
;CHECK-LABEL: {{^}}s_buffer_load_index_across_bb:
112112
;CHECK-NOT: s_waitcnt;
113-
;CHECK-NOT: v_or_b32
114-
;CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen offset:8
113+
;CHECK: v_or_b32
114+
;CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
115115
define amdgpu_ps void @s_buffer_load_index_across_bb(<4 x i32> inreg %desc, i32 %index) {
116116
main_body:
117117
%tmp = shl i32 %index, 4
@@ -127,8 +127,10 @@ bb1: ; preds = %main_body
127127

128128
;CHECK-LABEL: {{^}}s_buffer_load_index_across_bb_merged:
129129
;CHECK-NOT: s_waitcnt;
130-
;CHECK-NOT: v_or_b32
131-
;CHECK: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen offset:8
130+
;CHECK: v_or_b32
131+
;CHECK: v_or_b32
132+
;CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
133+
;CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
132134
define amdgpu_ps void @s_buffer_load_index_across_bb_merged(<4 x i32> inreg %desc, i32 %index) {
133135
main_body:
134136
%tmp = shl i32 %index, 4

‎llvm/test/CodeGen/ARM/atomic-op.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -183,11 +183,11 @@ entry:
183183
ret void
184184
}
185185

186-
define void @func2(i16 %int_val) nounwind {
186+
define void @func2() nounwind {
187187
entry:
188188
%val = alloca i16
189189
%old = alloca i16
190-
store i16 %int_val, i16* %val
190+
store i16 31, i16* %val
191191
; CHECK: ldrex
192192
; CHECK: cmp
193193
; CHECK: strex
@@ -197,7 +197,7 @@ entry:
197197
; CHECK-BAREMETAL-NOT: __sync
198198
%0 = atomicrmw umin i16* %val, i16 16 monotonic
199199
store i16 %0, i16* %old
200-
%uneg = sub i16 0, 2
200+
%uneg = sub i16 0, 1
201201
; CHECK: ldrex
202202
; CHECK: cmp
203203
; CHECK: strex
@@ -249,7 +249,7 @@ entry:
249249
; CHECK-T1-M0: bl ___sync_fetch_and_umin_1
250250
; CHECK-BAREMETAL: cmp
251251
; CHECK-BAREMETAL-NOT: __sync
252-
%uneg = sub i8 0, 2
252+
%uneg = sub i8 0, 1
253253
%1 = atomicrmw umin i8* %val, i8 %uneg monotonic
254254
store i8 %1, i8* %old
255255
; CHECK: ldrex

‎llvm/test/CodeGen/PowerPC/pr35688.ll

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -6,14 +6,16 @@
66
; Function Attrs: nounwind
77
define void @ec_GFp_nistp256_points_mul() {
88
; CHECK-LABEL: ec_GFp_nistp256_points_mul:
9-
; CHECK: ld 4, 0(3)
10-
; CHECK: li 3, 0
11-
; CHECK: subfic 5, 4, 0
12-
; CHECK: subfze 5, 3
9+
; CHECK: ld 5, 0(3)
10+
; CHECK: li 3, 127
11+
; CHECK: li 4, 0
12+
; CHECK: subfic 6, 5, 0
13+
; CHECK: subfze 6, 4
14+
; CHECK: sradi 7, 6, 63
15+
; CHECK: srad 6, 6, 3
16+
; CHECK: subfc 5, 5, 7
17+
; CHECK: subfe 5, 4, 6
1318
; CHECK: sradi 5, 5, 63
14-
; CHECK: subfc 4, 4, 5
15-
; CHECK: subfe 4, 3, 5
16-
; CHECK: sradi 4, 4, 63
1719

1820
; With MemorySSA, everything is taken out of the loop by licm.
1921
; Loads and stores to undef are treated as non-aliasing.

‎llvm/test/CodeGen/SystemZ/subregliveness-04.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -disable-early-taildup -disable-cgp -systemz-subreg-liveness < %s | FileCheck %s
22

33
; Check for successful compilation.
4-
; CHECK: lhi {{%r[0-9]+}}, -5
4+
; CHECK: lhi %r0, -5
55

66
target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
77
target triple = "s390x-ibm-linux"

‎llvm/test/CodeGen/X86/fold-tied-op.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,8 @@ target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
66
target triple = "i386--netbsd"
77

88
; CHECK-LABEL: fn1
9-
; CHECK: addl {{.*#+}} 4-byte Folded Reload
109
; CHECK: orl {{.*#+}} 4-byte Folded Reload
10+
; CHECK: addl {{.*#+}} 4-byte Folded Reload
1111
; CHECK: xorl {{.*#+}} 4-byte Folded Reload
1212
; CHECK: xorl {{.*#+}} 4-byte Folded Reload
1313
; CHECK: retl

‎llvm/test/CodeGen/X86/pr28444.ll

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,9 @@
1111
define void @extractelt_mismatch_vector_element_type(i32 %arg, i1 %x) {
1212
; CHECK-LABEL: extractelt_mismatch_vector_element_type:
1313
; CHECK: # %bb.0: # %bb
14-
; CHECK-NEXT: movb $1, (%rax)
15-
; CHECK-NEXT: movb $1, (%rax)
14+
; CHECK-NEXT: movb $1, %al
15+
; CHECK-NEXT: movb %al, (%rax)
16+
; CHECK-NEXT: movb %al, (%rax)
1617
; CHECK-NEXT: retq
1718
bb:
1819
%tmp = icmp ult i32 %arg, 0

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