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committedApr 9, 2019
[AArch64][GlobalISel] Add legalization for some vector G_SHL and G_ASHR.
This is needed for some future support for vector ICMP. Differential Revision: https://reviews.llvm.org/D60433 llvm-svn: 358033
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‎llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

+6
Original file line numberDiff line numberDiff line change
@@ -494,6 +494,12 @@ class LegalizeRuleSet {
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Types2);
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}
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LegalizeRuleSet &alwaysLegal() {
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using namespace LegalizeMutations;
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markAllTypeIdxsAsCovered();
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return actionIf(LegalizeAction::Legal, always);
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}
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/// The instruction is lowered.
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LegalizeRuleSet &lower() {
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using namespace LegalizeMutations;

‎llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp

+6-4
Original file line numberDiff line numberDiff line change
@@ -105,10 +105,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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.widenScalarToNextPow2(0);
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getActionDefinitionsBuilder({G_LSHR, G_ASHR})
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.legalFor({{s32, s32}, {s64, s64}})
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.clampScalar(1, s32, s64)
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.clampScalar(0, s32, s64)
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.minScalarSameAs(1, 0);
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.legalFor({{s32, s32}, {s64, s64}, {v2s32, v2s32}, {v4s32, v4s32}})
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.clampScalar(1, s32, s64)
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.clampScalar(0, s32, s64)
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.minScalarSameAs(1, 0);
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getActionDefinitionsBuilder({G_SREM, G_UREM})
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.lowerFor({s1, s8, s16, s32, s64});
@@ -273,6 +273,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
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.legalForCartesianProduct({s8, s16, s32, s64}, {s1, s8, s16, s32});
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getActionDefinitionsBuilder(G_TRUNC).alwaysLegal();
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// FP conversions
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getActionDefinitionsBuilder(G_FPTRUNC).legalFor(
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{{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}});

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir

+31
Original file line numberDiff line numberDiff line change
@@ -202,3 +202,34 @@ body: |
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$q0 = COPY %2
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...
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---
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name: test_ashr_v2i32
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body: |
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bb.0:
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; CHECK-LABEL: name: test_ashr_v2i32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
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; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s32>) = G_ASHR [[COPY]], [[COPY1]](<2 x s32>)
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; CHECK: $d0 = COPY [[ASHR]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $d0
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%1:_(<2 x s32>) = COPY $d1
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%2:_(<2 x s32>) = G_ASHR %0, %1
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$d0 = COPY %2
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...
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---
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name: test_ashr_v4i32
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body: |
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bb.0:
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; CHECK-LABEL: name: test_ashr_v4i32
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK: [[ASHR:%[0-9]+]]:_(<4 x s32>) = G_ASHR [[COPY]], [[COPY1]](<4 x s32>)
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; CHECK: $q0 = COPY [[ASHR]](<4 x s32>)
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = COPY $q1
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%2:_(<4 x s32>) = G_ASHR %0, %1
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$q0 = COPY %2
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...

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

+1-1
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@@ -160,7 +160,7 @@
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# DEBUG: .. the first uncovered type index: 2, OK
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#
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# DEBUG-NEXT: G_TRUNC (opcode {{[0-9]+}}): 2 type indices
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# DEBUG: .. type index coverage check SKIPPED: no rules defined
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# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
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#
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# DEBUG-NEXT: G_CONSTANT (opcode {{[0-9]+}}): 1 type index
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# DEBUG: .. the first uncovered type index: 1, OK

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