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jedilynjedilyn
committedDec 17, 2018
[Power9][NFC]update vabsd case for better dumping
Appended options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to get the more descriptive output. Also removed useless function attributes. llvm-svn: 349329
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‎llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll

+23-34
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,17 @@
1-
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
2-
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
3-
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-PWR8 -implicit-check-not vabsdu
1+
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s
2+
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s
3+
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-PWR8 -implicit-check-not vabsdu
44

5-
; Function Attrs: nounwind readnone
65
define <4 x i32> @simple_absv_32(<4 x i32> %a) local_unnamed_addr {
76
entry:
87
%sub.i = sub <4 x i32> zeroinitializer, %a
98
%0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %a, <4 x i32> %sub.i)
109
ret <4 x i32> %0
1110
; CHECK-LABEL: simple_absv_32
12-
; CHECK-DAG: vxor {{[0-9]+}}, [[REG:[0-9]+]], [[REG]]
13-
; CHECK-DAG: xvnegsp 34, 34
14-
; CHECK-DAG: xvnegsp 35, {{[0-9]+}}
15-
; CHECK-NEXT: vabsduw 2, 2, {{[0-9]+}}
11+
; CHECK-DAG: vxor v{{[0-9]+}}, v[[REG:[0-9]+]], v[[REG]]
12+
; CHECK-DAG: xvnegsp v2, v2
13+
; CHECK-DAG: xvnegsp v3, v{{[0-9]+}}
14+
; CHECK-NEXT: vabsduw v2, v2, v{{[0-9]+}}
1615
; CHECK-NEXT: blr
1716
; CHECK-PWR8-LABEL: simple_absv_32
1817
; CHECK-PWR8: xxlxor
@@ -21,17 +20,16 @@ entry:
2120
; CHECK-PWR8: blr
2221
}
2322

24-
; Function Attrs: nounwind readnone
2523
define <4 x i32> @simple_absv_32_swap(<4 x i32> %a) local_unnamed_addr {
2624
entry:
2725
%sub.i = sub <4 x i32> zeroinitializer, %a
2826
%0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub.i, <4 x i32> %a)
2927
ret <4 x i32> %0
3028
; CHECK-LABEL: simple_absv_32_swap
31-
; CHECK-DAG: vxor {{[0-9]+}}, [[REG:[0-9]+]], [[REG]]
32-
; CHECK-DAG: xvnegsp 34, 34
33-
; CHECK-DAG: xvnegsp 35, {{[0-9]+}}
34-
; CHECK-NEXT: vabsduw 2, 2, {{[0-9]+}}
29+
; CHECK-DAG: vxor v{{[0-9]+}}, v[[REG:[0-9]+]], v[[REG]]
30+
; CHECK-DAG: xvnegsp v2, v2
31+
; CHECK-DAG: xvnegsp v3, v{{[0-9]+}}
32+
; CHECK-NEXT: vabsduw v2, v2, v{{[0-9]+}}
3533
; CHECK-NEXT: blr
3634
; CHECK-PWR8-LABEL: simple_absv_32_swap
3735
; CHECK-PWR8: xxlxor
@@ -46,9 +44,9 @@ entry:
4644
%0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %a, <8 x i16> %sub.i)
4745
ret <8 x i16> %0
4846
; CHECK-LABEL: simple_absv_16
49-
; CHECK: mtvsrws {{[0-9]+}}, {{[0-9]+}}
50-
; CHECK-NEXT: vadduhm 2, 2, [[IMM:[0-9]+]]
51-
; CHECK-NEXT: vabsduh 2, 2, [[IMM]]
47+
; CHECK: mtvsrws v{{[0-9]+}}, r{{[0-9]+}}
48+
; CHECK-NEXT: vadduhm v2, v2, v[[IMM:[0-9]+]]
49+
; CHECK-NEXT: vabsduh v2, v2, v[[IMM]]
5250
; CHECK-NEXT: blr
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; CHECK-PWR8-LABEL: simple_absv_16
5452
; CHECK-PWR8: xxlxor
@@ -57,16 +55,15 @@ entry:
5755
; CHECK-PWR8: blr
5856
}
5957

60-
; Function Attrs: nounwind readnone
6158
define <16 x i8> @simple_absv_8(<16 x i8> %a) local_unnamed_addr {
6259
entry:
6360
%sub.i = sub <16 x i8> zeroinitializer, %a
6461
%0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %a, <16 x i8> %sub.i)
6562
ret <16 x i8> %0
6663
; CHECK-LABEL: simple_absv_8
67-
; CHECK: xxspltib {{[0-9]+}}, 128
68-
; CHECK-NEXT: vaddubm 2, 2, [[IMM:[0-9]+]]
69-
; CHECK-NEXT: vabsdub 2, 2, [[IMM]]
64+
; CHECK: xxspltib v{{[0-9]+}}, 128
65+
; CHECK-NEXT: vaddubm v2, v2, v[[IMM:[0-9]+]]
66+
; CHECK-NEXT: vabsdub v2, v2, v[[IMM]]
7067
; CHECK-NEXT: blr
7168
; CHECK-PWR8-LABEL: simple_absv_8
7269
; CHECK-PWR8: xxlxor
@@ -76,7 +73,6 @@ entry:
7673
}
7774

7875
; The select pattern can only be detected for v4i32.
79-
; Function Attrs: norecurse nounwind readnone
8076
define <4 x i32> @sub_absv_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
8177
entry:
8278
%0 = sub nsw <4 x i32> %a, %b
@@ -85,9 +81,9 @@ entry:
8581
%3 = select <4 x i1> %1, <4 x i32> %0, <4 x i32> %2
8682
ret <4 x i32> %3
8783
; CHECK-LABEL: sub_absv_32
88-
; CHECK-DAG: xvnegsp 34, 34
89-
; CHECK-DAG: xvnegsp 35, 35
90-
; CHECK-NEXT: vabsduw 2, 2, 3
84+
; CHECK-DAG: xvnegsp v3, v3
85+
; CHECK-DAG: xvnegsp v2, v2
86+
; CHECK-NEXT: vabsduw v2, v2, v3
9187
; CHECK-NEXT: blr
9288
; CHECK-PWR8-LABEL: sub_absv_32
9389
; CHECK-PWR8: vsubuwm
@@ -100,7 +96,6 @@ entry:
10096
; We do manage to find the word version of ABS but not the halfword.
10197
; Threfore, we end up doing more work than is required with a pair of abs for word
10298
; instead of just one for the halfword.
103-
; Function Attrs: norecurse nounwind readnone
10499
define <8 x i16> @sub_absv_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
105100
entry:
106101
%0 = sext <8 x i16> %a to <8 x i32>
@@ -303,15 +298,14 @@ entry:
303298
; CHECK-PWR8: blr
304299
}
305300

306-
; Function Attrs: nounwind readnone
307301
define <4 x i32> @sub_absv_vec_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
308302
entry:
309303
%sub = sub <4 x i32> %a, %b
310304
%sub.i = sub <4 x i32> zeroinitializer, %sub
311305
%0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub, <4 x i32> %sub.i)
312306
ret <4 x i32> %0
313307
; CHECK-LABEL: sub_absv_vec_32
314-
; CHECK: vabsduw 2, 2, 3
308+
; CHECK: vabsduw v2, v2, v3
315309
; CHECK-NEXT: blr
316310
; CHECK-PWR8-LABEL: sub_absv_vec_32
317311
; CHECK-PWR8: xxlxor
@@ -320,15 +314,14 @@ entry:
320314
; CHECK-PWR8: blr
321315
}
322316

323-
; Function Attrs: nounwind readnone
324317
define <8 x i16> @sub_absv_vec_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
325318
entry:
326319
%sub = sub <8 x i16> %a, %b
327320
%sub.i = sub <8 x i16> zeroinitializer, %sub
328321
%0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %sub, <8 x i16> %sub.i)
329322
ret <8 x i16> %0
330323
; CHECK-LABEL: sub_absv_vec_16
331-
; CHECK: vabsduh 2, 2, 3
324+
; CHECK: vabsduh v2, v2, v3
332325
; CHECK-NEXT: blr
333326
; CHECK-PWR8-LABEL: sub_absv_vec_16
334327
; CHECK-PWR8: xxlxor
@@ -337,15 +330,14 @@ entry:
337330
; CHECK-PWR8: blr
338331
}
339332

340-
; Function Attrs: nounwind readnone
341333
define <16 x i8> @sub_absv_vec_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
342334
entry:
343335
%sub = sub <16 x i8> %a, %b
344336
%sub.i = sub <16 x i8> zeroinitializer, %sub
345337
%0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %sub, <16 x i8> %sub.i)
346338
ret <16 x i8> %0
347339
; CHECK-LABEL: sub_absv_vec_8
348-
; CHECK: vabsdub 2, 2, 3
340+
; CHECK: vabsdub v2, v2, v3
349341
; CHECK-NEXT: blr
350342
; CHECK-PWR8-LABEL: sub_absv_vec_8
351343
; CHECK-PWR8: xxlxor
@@ -355,12 +347,9 @@ entry:
355347
}
356348

357349

358-
; Function Attrs: nounwind readnone
359350
declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>)
360351

361-
; Function Attrs: nounwind readnone
362352
declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>)
363353

364-
; Function Attrs: nounwind readnone
365354
declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>)
366355

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