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157 | 157 | // HBIN-DAG: [[P3:[0-9]+]]: backend, {[[P2]]}, assembler, (host-[[T]])
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158 | 158 | // HBIN-DAG: [[P4:[0-9]+]]: assembler, {[[P3]]}, object, (host-[[T]])
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159 | 159 | // HBIN-DAG: [[P5:[0-9]+]]: linker, {[[P4]]}, image, (host-[[T]])
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| 160 | +// HBIN-NOT: device |
160 | 161 | //
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161 | 162 | // Test single gpu architecture up to the assemble phase in host-only
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162 | 163 | // compilation mode.
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172 | 173 | // HASM-DAG: [[P1:[0-9]+]]: preprocessor, {[[P0]]}, [[T]]-cpp-output, (host-[[T]])
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173 | 174 | // HASM-DAG: [[P2:[0-9]+]]: compiler, {[[P1]]}, ir, (host-[[T]])
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174 | 175 | // HASM-DAG: [[P3:[0-9]+]]: backend, {[[P2]]}, assembler, (host-[[T]])
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| 176 | +// HASM-NOT: device |
175 | 177 |
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176 | 178 | //
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177 | 179 | // Test two gpu architectures with complete compilation in host-only
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190 | 192 | // HBIN2-DAG: [[P3:[0-9]+]]: backend, {[[P2]]}, assembler, (host-[[T]])
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191 | 193 | // HBIN2-DAG: [[P4:[0-9]+]]: assembler, {[[P3]]}, object, (host-[[T]])
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192 | 194 | // HBIN2-DAG: [[P5:[0-9]+]]: linker, {[[P4]]}, image, (host-[[T]])
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| 195 | +// HBIN2-NOT: device |
193 | 196 |
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194 | 197 | //
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195 | 198 | // Test two gpu architectures up to the assemble phase in host-only
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206 | 209 | // HASM2-DAG: [[P1:[0-9]+]]: preprocessor, {[[P0]]}, [[T]]-cpp-output, (host-[[T]])
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207 | 210 | // HASM2-DAG: [[P2:[0-9]+]]: compiler, {[[P1]]}, ir, (host-[[T]])
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208 | 211 | // HASM2-DAG: [[P3:[0-9]+]]: backend, {[[P2]]}, assembler, (host-[[T]])
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| 212 | +// HASM2-NOT: device |
209 | 213 |
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210 | 214 | //
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211 | 215 | // Test single gpu architecture with complete compilation in device-only
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224 | 228 | // DBIN_NV-DAG: [[P3:[0-9]+]]: backend, {[[P2]]}, assembler, (device-[[T]], [[ARCH]])
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225 | 229 | // DBIN_NV-DAG: [[P4:[0-9]+]]: assembler, {[[P3]]}, object, (device-[[T]], [[ARCH]])
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226 | 230 | // DBIN_NV-DAG: [[P5:[0-9]+]]: offload, "device-[[T]] (nvptx64-nvidia-cuda:[[ARCH]])" {[[P4]]}, object
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227 |
| - |
| 231 | +// DBIN-NOT: host |
228 | 232 | //
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229 | 233 | // Test single gpu architecture up to the assemble phase in device-only
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230 | 234 | // compilation mode.
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241 | 245 | // DASM-DAG: [[P2:[0-9]+]]: compiler, {[[P1]]}, ir, (device-[[T]], [[ARCH]])
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242 | 246 | // DASM_NV-DAG: [[P3:[0-9]+]]: backend, {[[P2]]}, assembler, (device-[[T]], [[ARCH]])
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243 | 247 | // DASM_NV-DAG: [[P4:[0-9]+]]: offload, "device-[[T]] ([[TRIPLE:nvptx64-nvidia-cuda|amdgcn-amd-amdhsa]]:[[ARCH]])" {[[P3]]}, assembler
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| 248 | +// DASM-NOT: host |
244 | 249 |
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245 | 250 | //
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246 | 251 | // Test two gpu architectures with complete compilation in device-only
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265 | 270 | // DBIN2_NV-DAG: [[P9:[0-9]+]]: backend, {[[P8]]}, assembler, (device-[[T]], [[ARCH2]])
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266 | 271 | // DBIN2_NV-DAG: [[P10:[0-9]+]]: assembler, {[[P9]]}, object, (device-[[T]], [[ARCH2]])
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267 | 272 | // DBIN2_NV-DAG: [[P11:[0-9]+]]: offload, "device-[[T]] ([[TRIPLE]]:[[ARCH2]])" {[[P10]]}, object
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268 |
| - |
| 273 | +// DBIN2-NOT: host |
269 | 274 | //
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270 | 275 | // Test two gpu architectures up to the assemble phase in device-only
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271 | 276 | // compilation mode.
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288 | 293 | // DASM2-DAG: [[P7:[0-9]+]]: compiler, {[[P6]]}, ir, (device-[[T]], [[ARCH2]])
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289 | 294 | // DASM2_NV-DAG: [[P8:[0-9]+]]: backend, {[[P7]]}, assembler, (device-[[T]], [[ARCH2]])
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290 | 295 | // DASM2_NV-DAG: [[P9:[0-9]+]]: offload, "device-[[T]] ([[TRIPLE]]:[[ARCH2]])" {[[P8]]}, assembler
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| 296 | +// DASM2-NOT: host |
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