Skip to content

Commit 11a332d

Browse files
tlivelytlively
committedOct 19, 2018
[WebAssembly] Handle undefined lane indices in SIMD patterns
Summary: Undefined indices in shuffles can be used when not all lanes of the output vector will be used. This happens for example in the expansion of vector reduce operations. Regardless, undefs are legal as lane indices in IR and should be supported. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53057 llvm-svn: 344803
·
llvmorg-21-initllvmorg-8.0.0-rc1
1 parent 2bfe759 commit 11a332d

File tree

3 files changed

+306
-2
lines changed

3 files changed

+306
-2
lines changed
 

‎llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

+4-2
Original file line numberDiff line numberDiff line change
@@ -990,8 +990,10 @@ WebAssemblyTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
990990
// Expand mask indices to byte indices and materialize them as operands
991991
for (size_t I = 0, Lanes = Mask.size(); I < Lanes; ++I) {
992992
for (size_t J = 0; J < LaneBytes; ++J) {
993-
Ops[OpIdx++] =
994-
DAG.getConstant((uint64_t)Mask[I] * LaneBytes + J, DL, MVT::i32);
993+
// Lower undefs (represented by -1 in mask) to zero
994+
uint64_t ByteIndex =
995+
Mask[I] == -1 ? 0 : (uint64_t)Mask[I] * LaneBytes + J;
996+
Ops[OpIdx++] = DAG.getConstant(ByteIndex, DL, MVT::i32);
995997
}
996998
}
997999

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

+36
Original file line numberDiff line numberDiff line change
@@ -181,6 +181,28 @@ def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
181181
def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
182182
(EXTRACT_LANE_v8i16_u V128:$vec, (i32 LaneIdx8:$idx))>;
183183

184+
// Lower undef lane indices to zero
185+
def : Pat<(and (i32 (vector_extract (v16i8 V128:$vec), undef)), (i32 0xff)),
186+
(EXTRACT_LANE_v16i8_u V128:$vec, 0)>;
187+
def : Pat<(and (i32 (vector_extract (v8i16 V128:$vec), undef)), (i32 0xffff)),
188+
(EXTRACT_LANE_v8i16_u V128:$vec, 0)>;
189+
def : Pat<(i32 (vector_extract (v16i8 V128:$vec), undef)),
190+
(EXTRACT_LANE_v16i8_u V128:$vec, 0)>;
191+
def : Pat<(i32 (vector_extract (v8i16 V128:$vec), undef)),
192+
(EXTRACT_LANE_v8i16_u V128:$vec, 0)>;
193+
def : Pat<(sext_inreg (i32 (vector_extract (v16i8 V128:$vec), undef)), i8),
194+
(EXTRACT_LANE_v16i8_s V128:$vec, 0)>;
195+
def : Pat<(sext_inreg (i32 (vector_extract (v8i16 V128:$vec), undef)), i16),
196+
(EXTRACT_LANE_v8i16_s V128:$vec, 0)>;
197+
def : Pat<(vector_extract (v4i32 V128:$vec), undef),
198+
(EXTRACT_LANE_v4i32 V128:$vec, 0)>;
199+
def : Pat<(vector_extract (v2i64 V128:$vec), undef),
200+
(EXTRACT_LANE_v2i64 V128:$vec, 0)>;
201+
def : Pat<(vector_extract (v4f32 V128:$vec), undef),
202+
(EXTRACT_LANE_v4f32 V128:$vec, 0)>;
203+
def : Pat<(vector_extract (v2f64 V128:$vec), undef),
204+
(EXTRACT_LANE_v2f64 V128:$vec, 0)>;
205+
184206
// Replace lane value: replace_lane
185207
multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t,
186208
WebAssemblyRegClass reg_t, ValueType lane_t,
@@ -201,6 +223,20 @@ defm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 20>;
201223
defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 21>;
202224
defm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 22>;
203225

226+
// Lower undef lane indices to zero
227+
def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef),
228+
(REPLACE_LANE_v16i8 V128:$vec, 0, I32:$x)>;
229+
def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef),
230+
(REPLACE_LANE_v8i16 V128:$vec, 0, I32:$x)>;
231+
def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef),
232+
(REPLACE_LANE_v4i32 V128:$vec, 0, I32:$x)>;
233+
def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef),
234+
(REPLACE_LANE_v2i64 V128:$vec, 0, I64:$x)>;
235+
def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef),
236+
(REPLACE_LANE_v4f32 V128:$vec, 0, F32:$x)>;
237+
def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef),
238+
(REPLACE_LANE_v2f64 V128:$vec, 0, F64:$x)>;
239+
204240
// Arbitrary other BUILD_VECTOR patterns
205241
def : Pat<(v16i8 (build_vector
206242
(i32 I32:$x0), (i32 I32:$x1), (i32 I32:$x2), (i32 I32:$x3),

‎llvm/test/CodeGen/WebAssembly/simd.ll

+266
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,18 @@ define i32 @extract_v16i8_s(<16 x i8> %v) {
5454
ret i32 %a
5555
}
5656

57+
; CHECK-LABEL: extract_undef_v16i8_s:
58+
; NO-SIMD128-NOT: i8x16
59+
; SIMD128-NEXT: .param v128{{$}}
60+
; SIMD128-NEXT: .result i32{{$}}
61+
; SIMD128-NEXT: i8x16.extract_lane_s $push[[R:[0-9]+]]=, $0, 0{{$}}
62+
; SIMD128-NEXT: return $pop[[R]]{{$}}
63+
define i32 @extract_undef_v16i8_s(<16 x i8> %v) {
64+
%elem = extractelement <16 x i8> %v, i8 undef
65+
%a = sext i8 %elem to i32
66+
ret i32 %a
67+
}
68+
5769
; CHECK-LABEL: extract_v16i8_u:
5870
; NO-SIMD128-NOT: i8x16
5971
; SIMD128-NEXT: .param v128{{$}}
@@ -66,6 +78,18 @@ define i32 @extract_v16i8_u(<16 x i8> %v) {
6678
ret i32 %a
6779
}
6880

81+
; CHECK-LABEL: extract_undef_v16i8_u:
82+
; NO-SIMD128-NOT: i8x16
83+
; SIMD128-NEXT: .param v128{{$}}
84+
; SIMD128-NEXT: .result i32{{$}}
85+
; SIMD128-NEXT: i8x16.extract_lane_u $push[[R:[0-9]+]]=, $0, 0{{$}}
86+
; SIMD128-NEXT: return $pop[[R]]{{$}}
87+
define i32 @extract_undef_v16i8_u(<16 x i8> %v) {
88+
%elem = extractelement <16 x i8> %v, i8 undef
89+
%a = zext i8 %elem to i32
90+
ret i32 %a
91+
}
92+
6993
; CHECK-LABEL: extract_v16i8:
7094
; NO-SIMD128-NOT: i8x16
7195
; SIMD128-NEXT: .param v128{{$}}
@@ -77,6 +101,17 @@ define i8 @extract_v16i8(<16 x i8> %v) {
77101
ret i8 %elem
78102
}
79103

104+
; CHECK-LABEL: extract_undef_v16i8:
105+
; NO-SIMD128-NOT: i8x16
106+
; SIMD128-NEXT: .param v128{{$}}
107+
; SIMD128-NEXT: .result i32{{$}}
108+
; SIMD128-NEXT: i8x16.extract_lane_u $push[[R:[0-9]+]]=, $0, 0{{$}}
109+
; SIMD128-NEXT: return $pop[[R]]{{$}}
110+
define i8 @extract_undef_v16i8(<16 x i8> %v) {
111+
%elem = extractelement <16 x i8> %v, i8 undef
112+
ret i8 %elem
113+
}
114+
80115
; CHECK-LABEL: replace_v16i8:
81116
; NO-SIMD128-NOT: i8x16
82117
; SIMD128-NEXT: .param v128, i32{{$}}
@@ -88,6 +123,17 @@ define <16 x i8> @replace_v16i8(<16 x i8> %v, i8 %x) {
88123
ret <16 x i8> %res
89124
}
90125

126+
; CHECK-LABEL: replace_undef_v16i8:
127+
; NO-SIMD128-NOT: i8x16
128+
; SIMD128-NEXT: .param v128, i32{{$}}
129+
; SIMD128-NEXT: .result v128{{$}}
130+
; SIMD128-NEXT: i8x16.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
131+
; SIMD128-NEXT: return $pop[[R]]{{$}}
132+
define <16 x i8> @replace_undef_v16i8(<16 x i8> %v, i8 %x) {
133+
%res = insertelement <16 x i8> %v, i8 %x, i32 undef
134+
ret <16 x i8> %res
135+
}
136+
91137
; CHECK-LABEL: shuffle_v16i8:
92138
; NO-SIMD128-NOT: v8x16
93139
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -102,6 +148,22 @@ define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
102148
ret <16 x i8> %res
103149
}
104150

151+
; CHECK-LABEL: shuffle_undef_v16i8:
152+
; NO-SIMD128-NOT: v8x16
153+
; SIMD128-NEXT: .param v128, v128{{$}}
154+
; SIMD128-NEXT: .result v128{{$}}
155+
; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
156+
; SIMD128-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
157+
; SIMD128-NEXT: return $pop[[R]]{{$}}
158+
define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
159+
%res = shufflevector <16 x i8> %x, <16 x i8> %y,
160+
<16 x i32> <i32 1, i32 undef, i32 undef, i32 undef,
161+
i32 undef, i32 undef, i32 undef, i32 undef,
162+
i32 undef, i32 undef, i32 undef, i32 undef,
163+
i32 undef, i32 undef, i32 undef, i32 undef>
164+
ret <16 x i8> %res
165+
}
166+
105167
; CHECK-LABEL: build_v16i8:
106168
; NO-SIMD128-NOT: i8x16
107169
; SIMD128-NEXT: .param i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32{{$}}
@@ -190,6 +252,18 @@ define i32 @extract_v8i16_s(<8 x i16> %v) {
190252
ret i32 %a
191253
}
192254

255+
; CHECK-LABEL: extract_undef_v8i16_s:
256+
; NO-SIMD128-NOT: i16x8
257+
; SIMD128-NEXT: .param v128{{$}}
258+
; SIMD128-NEXT: .result i32{{$}}
259+
; SIMD128-NEXT: i16x8.extract_lane_s $push[[R:[0-9]+]]=, $0, 0{{$}}
260+
; SIMD128-NEXT: return $pop[[R]]{{$}}
261+
define i32 @extract_undef_v8i16_s(<8 x i16> %v) {
262+
%elem = extractelement <8 x i16> %v, i16 undef
263+
%a = sext i16 %elem to i32
264+
ret i32 %a
265+
}
266+
193267
; CHECK-LABEL: extract_v8i16_u:
194268
; NO-SIMD128-NOT: i16x8
195269
; SIMD128-NEXT: .param v128{{$}}
@@ -202,6 +276,18 @@ define i32 @extract_v8i16_u(<8 x i16> %v) {
202276
ret i32 %a
203277
}
204278

279+
; CHECK-LABEL: extract_undef_v8i16_u:
280+
; NO-SIMD128-NOT: i16x8
281+
; SIMD128-NEXT: .param v128{{$}}
282+
; SIMD128-NEXT: .result i32{{$}}
283+
; SIMD128-NEXT: i16x8.extract_lane_u $push[[R:[0-9]+]]=, $0, 0{{$}}
284+
; SIMD128-NEXT: return $pop[[R]]{{$}}
285+
define i32 @extract_undef_v8i16_u(<8 x i16> %v) {
286+
%elem = extractelement <8 x i16> %v, i16 undef
287+
%a = zext i16 %elem to i32
288+
ret i32 %a
289+
}
290+
205291
; CHECK-LABEL: extract_v8i16:
206292
; NO-SIMD128-NOT: i16x8
207293
; SIMD128-NEXT: .param v128{{$}}
@@ -213,6 +299,17 @@ define i16 @extract_v8i16(<8 x i16> %v) {
213299
ret i16 %elem
214300
}
215301

302+
; CHECK-LABEL: extract_undef_v8i16:
303+
; NO-SIMD128-NOT: i16x8
304+
; SIMD128-NEXT: .param v128{{$}}
305+
; SIMD128-NEXT: .result i32{{$}}
306+
; SIMD128-NEXT: i16x8.extract_lane_u $push[[R:[0-9]+]]=, $0, 0{{$}}
307+
; SIMD128-NEXT: return $pop[[R]]{{$}}
308+
define i16 @extract_undef_v8i16(<8 x i16> %v) {
309+
%elem = extractelement <8 x i16> %v, i16 undef
310+
ret i16 %elem
311+
}
312+
216313
; CHECK-LABEL: replace_v8i16:
217314
; NO-SIMD128-NOT: i16x8
218315
; SIMD128-NEXT: .param v128, i32{{$}}
@@ -224,6 +321,17 @@ define <8 x i16> @replace_v8i16(<8 x i16> %v, i16 %x) {
224321
ret <8 x i16> %res
225322
}
226323

324+
; CHECK-LABEL: replace_undef_v8i16:
325+
; NO-SIMD128-NOT: i16x8
326+
; SIMD128-NEXT: .param v128, i32{{$}}
327+
; SIMD128-NEXT: .result v128{{$}}
328+
; SIMD128-NEXT: i16x8.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
329+
; SIMD128-NEXT: return $pop[[R]]{{$}}
330+
define <8 x i16> @replace_undef_v8i16(<8 x i16> %v, i16 %x) {
331+
%res = insertelement <8 x i16> %v, i16 %x, i32 undef
332+
ret <8 x i16> %res
333+
}
334+
227335
; CHECK-LABEL: shuffle_v8i16:
228336
; NO-SIMD128-NOT: v8x16
229337
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -237,6 +345,20 @@ define <8 x i16> @shuffle_v8i16(<8 x i16> %x, <8 x i16> %y) {
237345
ret <8 x i16> %res
238346
}
239347

348+
; CHECK-LABEL: shuffle_undef_v8i16:
349+
; NO-SIMD128-NOT: v8x16
350+
; SIMD128-NEXT: .param v128, v128{{$}}
351+
; SIMD128-NEXT: .result v128{{$}}
352+
; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
353+
; SIMD128-SAME: 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
354+
; SIMD128-NEXT: return $pop[[R]]{{$}}
355+
define <8 x i16> @shuffle_undef_v8i16(<8 x i16> %x, <8 x i16> %y) {
356+
%res = shufflevector <8 x i16> %x, <8 x i16> %y,
357+
<8 x i32> <i32 1, i32 undef, i32 undef, i32 undef,
358+
i32 undef, i32 undef, i32 undef, i32 undef>
359+
ret <8 x i16> %res
360+
}
361+
240362
; CHECK-LABEL: build_v8i16:
241363
; NO-SIMD128-NOT: i16x8
242364
; SIMD128-NEXT: .param i32, i32, i32, i32, i32, i32, i32, i32{{$}}
@@ -305,6 +427,17 @@ define i32 @extract_v4i32(<4 x i32> %v) {
305427
ret i32 %elem
306428
}
307429

430+
; CHECK-LABEL: extract_undef_v4i32:
431+
; NO-SIMD128-NOT: i32x4
432+
; SIMD128-NEXT: .param v128{{$}}
433+
; SIMD128-NEXT: .result i32{{$}}
434+
; SIMD128-NEXT: i32x4.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}}
435+
; SIMD128-NEXT: return $pop[[R]]{{$}}
436+
define i32 @extract_undef_v4i32(<4 x i32> %v) {
437+
%elem = extractelement <4 x i32> %v, i32 undef
438+
ret i32 %elem
439+
}
440+
308441
; CHECK-LABEL: replace_v4i32:
309442
; NO-SIMD128-NOT: i32x4
310443
; SIMD128-NEXT: .param v128, i32{{$}}
@@ -316,6 +449,17 @@ define <4 x i32> @replace_v4i32(<4 x i32> %v, i32 %x) {
316449
ret <4 x i32> %res
317450
}
318451

452+
; CHECK-LABEL: replace_undef_v4i32:
453+
; NO-SIMD128-NOT: i32x4
454+
; SIMD128-NEXT: .param v128, i32{{$}}
455+
; SIMD128-NEXT: .result v128{{$}}
456+
; SIMD128-NEXT: i32x4.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
457+
; SIMD128-NEXT: return $pop[[R]]{{$}}
458+
define <4 x i32> @replace_undef_v4i32(<4 x i32> %v, i32 %x) {
459+
%res = insertelement <4 x i32> %v, i32 %x, i32 undef
460+
ret <4 x i32> %res
461+
}
462+
319463
; CHECK-LABEL: shuffle_v4i32:
320464
; NO-SIMD128-NOT: v8x16
321465
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -329,6 +473,19 @@ define <4 x i32> @shuffle_v4i32(<4 x i32> %x, <4 x i32> %y) {
329473
ret <4 x i32> %res
330474
}
331475

476+
; CHECK-LABEL: shuffle_undef_v4i32:
477+
; NO-SIMD128-NOT: v8x16
478+
; SIMD128-NEXT: .param v128, v128{{$}}
479+
; SIMD128-NEXT: .result v128{{$}}
480+
; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
481+
; SIMD128-SAME: 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
482+
; SIMD128-NEXT: return $pop[[R]]{{$}}
483+
define <4 x i32> @shuffle_undef_v4i32(<4 x i32> %x, <4 x i32> %y) {
484+
%res = shufflevector <4 x i32> %x, <4 x i32> %y,
485+
<4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
486+
ret <4 x i32> %res
487+
}
488+
332489
; CHECK-LABEL: build_v4i32:
333490
; NO-SIMD128-NOT: i32x4
334491
; SIMD128-NEXT: .param i32, i32, i32, i32{{$}}
@@ -390,6 +547,18 @@ define i64 @extract_v2i64(<2 x i64> %v) {
390547
ret i64 %elem
391548
}
392549

550+
; CHECK-LABEL: extract_undef_v2i64:
551+
; NO-SIMD128-NOT: i64x2
552+
; SIMD128-VM-NOT: i64x2
553+
; SIMD128-NEXT: .param v128{{$}}
554+
; SIMD128-NEXT: .result i64{{$}}
555+
; SIMD128-NEXT: i64x2.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}}
556+
; SIMD128-NEXT: return $pop[[R]]{{$}}
557+
define i64 @extract_undef_v2i64(<2 x i64> %v) {
558+
%elem = extractelement <2 x i64> %v, i64 undef
559+
ret i64 %elem
560+
}
561+
393562
; CHECK-LABEL: replace_v2i64:
394563
; NO-SIMD128-NOT: i64x2
395564
; SIMD128-VM-NOT: i64x2
@@ -402,6 +571,18 @@ define <2 x i64> @replace_v2i64(<2 x i64> %v, i64 %x) {
402571
ret <2 x i64> %res
403572
}
404573

574+
; CHECK-LABEL: replace_undef_v2i64:
575+
; NO-SIMD128-NOT: i64x2
576+
; SIMD128-VM-NOT: i64x2
577+
; SIMD128-NEXT: .param v128, i64{{$}}
578+
; SIMD128-NEXT: .result v128{{$}}
579+
; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
580+
; SIMD128-NEXT: return $pop[[R]]{{$}}
581+
define <2 x i64> @replace_undef_v2i64(<2 x i64> %v, i64 %x) {
582+
%res = insertelement <2 x i64> %v, i64 %x, i32 undef
583+
ret <2 x i64> %res
584+
}
585+
405586
; CHECK-LABEL: shuffle_v2i64:
406587
; NO-SIMD128-NOT: v8x16
407588
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -414,6 +595,19 @@ define <2 x i64> @shuffle_v2i64(<2 x i64> %x, <2 x i64> %y) {
414595
ret <2 x i64> %res
415596
}
416597

598+
; CHECK-LABEL: shuffle_undef_v2i64:
599+
; NO-SIMD128-NOT: v8x16
600+
; SIMD128-NEXT: .param v128, v128{{$}}
601+
; SIMD128-NEXT: .result v128{{$}}
602+
; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
603+
; SIMD128-SAME: 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
604+
; SIMD128-NEXT: return $pop[[R]]{{$}}
605+
define <2 x i64> @shuffle_undef_v2i64(<2 x i64> %x, <2 x i64> %y) {
606+
%res = shufflevector <2 x i64> %x, <2 x i64> %y,
607+
<2 x i32> <i32 1, i32 undef>
608+
ret <2 x i64> %res
609+
}
610+
417611
; CHECK-LABEL: build_v2i64:
418612
; NO-SIMD128-NOT: i64x2
419613
; SIMD128-VM-NOT: i64x2
@@ -472,6 +666,17 @@ define float @extract_v4f32(<4 x float> %v) {
472666
ret float %elem
473667
}
474668

669+
; CHECK-LABEL: extract_undef_v4f32:
670+
; NO-SIMD128-NOT: f32x4
671+
; SIMD128-NEXT: .param v128{{$}}
672+
; SIMD128-NEXT: .result f32{{$}}
673+
; SIMD128-NEXT: f32x4.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}}
674+
; SIMD128-NEXT: return $pop[[R]]{{$}}
675+
define float @extract_undef_v4f32(<4 x float> %v) {
676+
%elem = extractelement <4 x float> %v, i32 undef
677+
ret float %elem
678+
}
679+
475680
; CHECK-LABEL: replace_v4f32:
476681
; NO-SIMD128-NOT: f32x4
477682
; SIMD128-NEXT: .param v128, f32{{$}}
@@ -483,6 +688,17 @@ define <4 x float> @replace_v4f32(<4 x float> %v, float %x) {
483688
ret <4 x float> %res
484689
}
485690

691+
; CHECK-LABEL: replace_undef_v4f32:
692+
; NO-SIMD128-NOT: f32x4
693+
; SIMD128-NEXT: .param v128, f32{{$}}
694+
; SIMD128-NEXT: .result v128{{$}}
695+
; SIMD128-NEXT: f32x4.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
696+
; SIMD128-NEXT: return $pop[[R]]{{$}}
697+
define <4 x float> @replace_undef_v4f32(<4 x float> %v, float %x) {
698+
%res = insertelement <4 x float> %v, float %x, i32 undef
699+
ret <4 x float> %res
700+
}
701+
486702
; CHECK-LABEL: shuffle_v4f32:
487703
; NO-SIMD128-NOT: v8x16
488704
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -496,6 +712,19 @@ define <4 x float> @shuffle_v4f32(<4 x float> %x, <4 x float> %y) {
496712
ret <4 x float> %res
497713
}
498714

715+
; CHECK-LABEL: shuffle_undef_v4f32:
716+
; NO-SIMD128-NOT: v8x16
717+
; SIMD128-NEXT: .param v128, v128{{$}}
718+
; SIMD128-NEXT: .result v128{{$}}
719+
; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
720+
; SIMD128-SAME: 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
721+
; SIMD128-NEXT: return $pop[[R]]{{$}}
722+
define <4 x float> @shuffle_undef_v4f32(<4 x float> %x, <4 x float> %y) {
723+
%res = shufflevector <4 x float> %x, <4 x float> %y,
724+
<4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
725+
ret <4 x float> %res
726+
}
727+
499728
; CHECK-LABEL: build_v4f32:
500729
; NO-SIMD128-NOT: f32x4
501730
; SIMD128-NEXT: .param f32, f32, f32, f32{{$}}
@@ -556,6 +785,18 @@ define double @extract_v2f64(<2 x double> %v) {
556785
ret double %elem
557786
}
558787

788+
; CHECK-LABEL: extract_undef_v2f64:
789+
; NO-SIMD128-NOT: f64x2
790+
; SIMD128-VM-NOT: f64x2
791+
; SIMD128-NEXT: .param v128{{$}}
792+
; SIMD128-NEXT: .result f64{{$}}
793+
; SIMD128-NEXT: f64x2.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}}
794+
; SIMD128-NEXT: return $pop[[R]]{{$}}
795+
define double @extract_undef_v2f64(<2 x double> %v) {
796+
%elem = extractelement <2 x double> %v, i32 undef
797+
ret double %elem
798+
}
799+
559800
; CHECK-LABEL: replace_v2f64:
560801
; NO-SIMD128-NOT: f64x2
561802
; SIMD128-VM-NOT: f64x2
@@ -568,6 +809,18 @@ define <2 x double> @replace_v2f64(<2 x double> %v, double %x) {
568809
ret <2 x double> %res
569810
}
570811

812+
; CHECK-LABEL: replace_undef_v2f64:
813+
; NO-SIMD128-NOT: f64x2
814+
; SIMD128-VM-NOT: f64x2
815+
; SIMD128-NEXT: .param v128, f64{{$}}
816+
; SIMD128-NEXT: .result v128{{$}}
817+
; SIMD128-NEXT: f64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
818+
; SIMD128-NEXT: return $pop[[R]]{{$}}
819+
define <2 x double> @replace_undef_v2f64(<2 x double> %v, double %x) {
820+
%res = insertelement <2 x double> %v, double %x, i32 undef
821+
ret <2 x double> %res
822+
}
823+
571824
; CHECK-LABEL: shuffle_v2f64:
572825
; NO-SIMD128-NOT: v8x16
573826
; SIMD128-NEXT: .param v128, v128{{$}}
@@ -581,6 +834,19 @@ define <2 x double> @shuffle_v2f64(<2 x double> %x, <2 x double> %y) {
581834
ret <2 x double> %res
582835
}
583836

837+
; CHECK-LABEL: shuffle_undef_v2f64:
838+
; NO-SIMD128-NOT: v8x16
839+
; SIMD128-NEXT: .param v128, v128{{$}}
840+
; SIMD128-NEXT: .result v128{{$}}
841+
; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
842+
; SIMD128-SAME: 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
843+
; SIMD128-NEXT: return $pop[[R]]{{$}}
844+
define <2 x double> @shuffle_undef_v2f64(<2 x double> %x, <2 x double> %y) {
845+
%res = shufflevector <2 x double> %x, <2 x double> %y,
846+
<2 x i32> <i32 1, i32 undef>
847+
ret <2 x double> %res
848+
}
849+
584850
; CHECK-LABEL: build_v2f64:
585851
; NO-SIMD128-NOT: f64x2
586852
; SIMD128-VM-NOT: f64x2

0 commit comments

Comments
 (0)
Please sign in to comment.