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tlivelytlively
committedOct 13, 2018
[WebAssembly][NFC] Unify ARGUMENT classes
Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D53172 llvm-svn: 344436
·
llvmorg-21-initllvmorg-8.0.0-rc1
1 parent 74c6aaf commit 0ff82ac

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5 files changed

+36
-45
lines changed

5 files changed

+36
-45
lines changed
 

‎llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

+8-8
Original file line numberDiff line numberDiff line change
@@ -176,14 +176,14 @@ void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
176176
LLVM_DEBUG(dbgs() << "EmitInstruction: " << *MI << '\n');
177177

178178
switch (MI->getOpcode()) {
179-
case WebAssembly::ARGUMENT_I32:
180-
case WebAssembly::ARGUMENT_I32_S:
181-
case WebAssembly::ARGUMENT_I64:
182-
case WebAssembly::ARGUMENT_I64_S:
183-
case WebAssembly::ARGUMENT_F32:
184-
case WebAssembly::ARGUMENT_F32_S:
185-
case WebAssembly::ARGUMENT_F64:
186-
case WebAssembly::ARGUMENT_F64_S:
179+
case WebAssembly::ARGUMENT_i32:
180+
case WebAssembly::ARGUMENT_i32_S:
181+
case WebAssembly::ARGUMENT_i64:
182+
case WebAssembly::ARGUMENT_i64_S:
183+
case WebAssembly::ARGUMENT_f32:
184+
case WebAssembly::ARGUMENT_f32_S:
185+
case WebAssembly::ARGUMENT_f64:
186+
case WebAssembly::ARGUMENT_f64_S:
187187
case WebAssembly::ARGUMENT_v16i8:
188188
case WebAssembly::ARGUMENT_v16i8_S:
189189
case WebAssembly::ARGUMENT_v8i16:

‎llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp

+5-5
Original file line numberDiff line numberDiff line change
@@ -646,19 +646,19 @@ bool WebAssemblyFastISel::fastLowerArguments() {
646646
case MVT::i8:
647647
case MVT::i16:
648648
case MVT::i32:
649-
Opc = WebAssembly::ARGUMENT_I32;
649+
Opc = WebAssembly::ARGUMENT_i32;
650650
RC = &WebAssembly::I32RegClass;
651651
break;
652652
case MVT::i64:
653-
Opc = WebAssembly::ARGUMENT_I64;
653+
Opc = WebAssembly::ARGUMENT_i64;
654654
RC = &WebAssembly::I64RegClass;
655655
break;
656656
case MVT::f32:
657-
Opc = WebAssembly::ARGUMENT_F32;
657+
Opc = WebAssembly::ARGUMENT_f32;
658658
RC = &WebAssembly::F32RegClass;
659659
break;
660660
case MVT::f64:
661-
Opc = WebAssembly::ARGUMENT_F64;
661+
Opc = WebAssembly::ARGUMENT_f64;
662662
RC = &WebAssembly::F64RegClass;
663663
break;
664664
case MVT::v16i8:
@@ -686,7 +686,7 @@ bool WebAssemblyFastISel::fastLowerArguments() {
686686
RC = &WebAssembly::V128RegClass;
687687
break;
688688
case MVT::ExceptRef:
689-
Opc = WebAssembly::ARGUMENT_EXCEPT_REF;
689+
Opc = WebAssembly::ARGUMENT_ExceptRef;
690690
RC = &WebAssembly::EXCEPT_REFRegClass;
691691
break;
692692
default:

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td

+9-9
Original file line numberDiff line numberDiff line change
@@ -163,18 +163,18 @@ include "WebAssemblyInstrFormats.td"
163163
// Additional instructions.
164164
//===----------------------------------------------------------------------===//
165165

166-
multiclass ARGUMENT<WebAssemblyRegClass vt> {
166+
multiclass ARGUMENT<WebAssemblyRegClass reg, ValueType vt> {
167167
let hasSideEffects = 1, isCodeGenOnly = 1,
168168
Defs = []<Register>, Uses = [ARGUMENTS] in
169-
defm ARGUMENT_#vt : I<(outs vt:$res), (ins i32imm:$argno),
170-
(outs), (ins i32imm:$argno),
171-
[(set vt:$res, (WebAssemblyargument timm:$argno))]>;
169+
defm ARGUMENT_#vt :
170+
I<(outs reg:$res), (ins i32imm:$argno), (outs), (ins i32imm:$argno),
171+
[(set (vt reg:$res), (WebAssemblyargument timm:$argno))]>;
172172
}
173-
defm "": ARGUMENT<I32>;
174-
defm "": ARGUMENT<I64>;
175-
defm "": ARGUMENT<F32>;
176-
defm "": ARGUMENT<F64>;
177-
defm "": ARGUMENT<EXCEPT_REF>;
173+
defm "": ARGUMENT<I32, i32>;
174+
defm "": ARGUMENT<I64, i64>;
175+
defm "": ARGUMENT<F32, f32>;
176+
defm "": ARGUMENT<F64, f64>;
177+
defm "": ARGUMENT<EXCEPT_REF, ExceptRef>;
178178

179179
// get_local and set_local are not generated by instruction selection; they
180180
// are implied by virtual register uses and defs.

‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

+6-15
Original file line numberDiff line numberDiff line change
@@ -21,21 +21,12 @@ multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
2121
Requires<[HasSIMD128]>;
2222
}
2323

24-
multiclass SIMD_ARGUMENT<ValueType vt> {
25-
let hasSideEffects = 1, isCodeGenOnly = 1,
26-
Defs = []<Register>, Uses = [ARGUMENTS] in
27-
defm ARGUMENT_#vt : SIMD_I<(outs V128:$res), (ins i32imm:$argno),
28-
(outs), (ins i32imm:$argno),
29-
[(set (vt V128:$res),
30-
(WebAssemblyargument timm:$argno))]>;
31-
}
32-
33-
defm "": SIMD_ARGUMENT<v16i8>;
34-
defm "": SIMD_ARGUMENT<v8i16>;
35-
defm "": SIMD_ARGUMENT<v4i32>;
36-
defm "": SIMD_ARGUMENT<v2i64>;
37-
defm "": SIMD_ARGUMENT<v4f32>;
38-
defm "": SIMD_ARGUMENT<v2f64>;
24+
defm "" : ARGUMENT<V128, v16i8>;
25+
defm "" : ARGUMENT<V128, v8i16>;
26+
defm "" : ARGUMENT<V128, v4i32>;
27+
defm "" : ARGUMENT<V128, v2i64>;
28+
defm "" : ARGUMENT<V128, v4f32>;
29+
defm "" : ARGUMENT<V128, v2f64>;
3930

4031
// Constrained immediate argument types
4132
foreach SIZE = [8, 16] in

‎llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp

+8-8
Original file line numberDiff line numberDiff line change
@@ -27,14 +27,14 @@ const char *const WebAssembly::PersonalityWrapperFn =
2727

2828
bool WebAssembly::isArgument(const MachineInstr &MI) {
2929
switch (MI.getOpcode()) {
30-
case WebAssembly::ARGUMENT_I32:
31-
case WebAssembly::ARGUMENT_I32_S:
32-
case WebAssembly::ARGUMENT_I64:
33-
case WebAssembly::ARGUMENT_I64_S:
34-
case WebAssembly::ARGUMENT_F32:
35-
case WebAssembly::ARGUMENT_F32_S:
36-
case WebAssembly::ARGUMENT_F64:
37-
case WebAssembly::ARGUMENT_F64_S:
30+
case WebAssembly::ARGUMENT_i32:
31+
case WebAssembly::ARGUMENT_i32_S:
32+
case WebAssembly::ARGUMENT_i64:
33+
case WebAssembly::ARGUMENT_i64_S:
34+
case WebAssembly::ARGUMENT_f32:
35+
case WebAssembly::ARGUMENT_f32_S:
36+
case WebAssembly::ARGUMENT_f64:
37+
case WebAssembly::ARGUMENT_f64_S:
3838
case WebAssembly::ARGUMENT_v16i8:
3939
case WebAssembly::ARGUMENT_v16i8_S:
4040
case WebAssembly::ARGUMENT_v8i16:

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