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topperctopperc
committedOct 3, 2018
[X86] Stop promoting vector ISD::SELECT to vXi64.
The additional patterns needed for this aren't overwhelming and introducing extra bitcasts during lowering limits our ability to do computeNumSignBits. Not that I have a good example of that for select. I'm just becoming increasingly grumpy about promotion of AND/OR/XOR. SELECT was just a lot easier to fix. llvm-svn: 343723
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2 files changed

+41
-3
lines changed

2 files changed

+41
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‎llvm/lib/Target/X86/X86ISelLowering.cpp

+9-3
Original file line numberDiff line numberDiff line change
@@ -876,12 +876,14 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
876876
setOperationPromotedToType(ISD::OR, VT, MVT::v2i64);
877877
setOperationPromotedToType(ISD::XOR, VT, MVT::v2i64);
878878
setOperationPromotedToType(ISD::LOAD, VT, MVT::v2i64);
879-
setOperationPromotedToType(ISD::SELECT, VT, MVT::v2i64);
880879
}
881880

882881
// Custom lower v2i64 and v2f64 selects.
883882
setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
884883
setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
884+
setOperationAction(ISD::SELECT, MVT::v4i32, Custom);
885+
setOperationAction(ISD::SELECT, MVT::v8i16, Custom);
886+
setOperationAction(ISD::SELECT, MVT::v16i8, Custom);
885887

886888
setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
887889
setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
@@ -1058,6 +1060,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
10581060

10591061
setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
10601062
setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1063+
setOperationAction(ISD::SELECT, MVT::v8i32, Custom);
1064+
setOperationAction(ISD::SELECT, MVT::v16i16, Custom);
1065+
setOperationAction(ISD::SELECT, MVT::v32i8, Custom);
10611066
setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
10621067

10631068
for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
@@ -1174,7 +1179,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
11741179
setOperationPromotedToType(ISD::OR, VT, MVT::v4i64);
11751180
setOperationPromotedToType(ISD::XOR, VT, MVT::v4i64);
11761181
setOperationPromotedToType(ISD::LOAD, VT, MVT::v4i64);
1177-
setOperationPromotedToType(ISD::SELECT, VT, MVT::v4i64);
11781182
}
11791183

11801184
if (HasInt256) {
@@ -1347,6 +1351,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
13471351

13481352
setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
13491353
setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1354+
setOperationAction(ISD::SELECT, MVT::v16i32, Custom);
1355+
setOperationAction(ISD::SELECT, MVT::v32i16, Custom);
1356+
setOperationAction(ISD::SELECT, MVT::v64i8, Custom);
13501357
setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
13511358

13521359
for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
@@ -1421,7 +1428,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
14211428
}
14221429
for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
14231430
setOperationPromotedToType(ISD::LOAD, VT, MVT::v8i64);
1424-
setOperationPromotedToType(ISD::SELECT, VT, MVT::v8i64);
14251431
}
14261432

14271433
// Need to custom split v32i16/v64i8 bitcasts.

‎llvm/lib/Target/X86/X86InstrCompiler.td

+32
Original file line numberDiff line numberDiff line change
@@ -611,26 +611,58 @@ def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
611611
(CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
612612

613613
let Predicates = [NoVLX] in {
614+
def : Pat<(v16i8 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
615+
(CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
616+
def : Pat<(v8i16 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
617+
(CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
618+
def : Pat<(v4i32 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
619+
(CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
614620
def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
615621
(CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
616622
def : Pat<(v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
617623
(CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
624+
625+
def : Pat<(v32i8 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)),
626+
(CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>;
627+
def : Pat<(v16i16 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)),
628+
(CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>;
629+
def : Pat<(v8i32 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)),
630+
(CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>;
618631
def : Pat<(v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)),
619632
(CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>;
620633
def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)),
621634
(CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>;
622635
}
623636
let Predicates = [HasVLX] in {
637+
def : Pat<(v16i8 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)),
638+
(CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>;
639+
def : Pat<(v8i16 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)),
640+
(CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>;
641+
def : Pat<(v4i32 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)),
642+
(CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>;
624643
def : Pat<(v4f32 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)),
625644
(CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>;
626645
def : Pat<(v2f64 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)),
627646
(CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>;
647+
648+
def : Pat<(v32i8 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)),
649+
(CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>;
650+
def : Pat<(v16i16 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)),
651+
(CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>;
652+
def : Pat<(v8i32 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)),
653+
(CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>;
628654
def : Pat<(v8f32 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)),
629655
(CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>;
630656
def : Pat<(v4f64 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)),
631657
(CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>;
632658
}
633659

660+
def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)),
661+
(CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>;
662+
def : Pat<(v32i16 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)),
663+
(CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>;
664+
def : Pat<(v16i32 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)),
665+
(CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>;
634666
def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)),
635667
(CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>;
636668
def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)),

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