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ostannardostannard
committedSep 27, 2018
[AArch64][v8.5A] Add FRINT[32,64][Z,X] instructions
These are some new variants of the "Floating-point Round to Integral" family of instructions, which round to the nearest floating-point value which fits in a 32- or 64-bit integer. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52475 llvm-svn: 343209
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‎llvm/lib/Target/AArch64/AArch64.td

+8-2
Original file line numberDiff line numberDiff line change
@@ -207,6 +207,10 @@ def FeatureAggressiveFMA :
207207
def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
208208
"Enable alternative NZCV format for floating point comparisons">;
209209

210+
def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
211+
"Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
212+
"an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
213+
210214
//===----------------------------------------------------------------------===//
211215
// Architectures.
212216
//
@@ -223,8 +227,10 @@ def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
223227
def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
224228
"Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>;
225229

226-
def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
227-
"Support ARM v8.5a instructions", [HasV8_4aOps, FeatureAltFPCmp]>;
230+
def HasV8_5aOps : SubtargetFeature<
231+
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
232+
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264]
233+
>;
228234

229235
//===----------------------------------------------------------------------===//
230236
// Register File Description

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td

+36-1
Original file line numberDiff line numberDiff line change
@@ -4433,6 +4433,22 @@ multiclass SingleOperandFPData<bits<4> opcode, string asm,
44334433
}
44344434
}
44354435

4436+
multiclass SingleOperandFPNo16<bits<6> opcode, string asm,
4437+
SDPatternOperator node = null_frag>{
4438+
4439+
def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
4440+
let Inst{23-22} = 0b00; // 32-bit registers
4441+
}
4442+
4443+
def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
4444+
let Inst{23-22} = 0b01; // 64-bit registers
4445+
}
4446+
}
4447+
4448+
// FRInt[32|64][Z|N] instructions
4449+
multiclass FRIntNNT<bits<2> opcode, string asm, SDPatternOperator node = null_frag> :
4450+
SingleOperandFPNo16<{0b0100,opcode}, asm, node>;
4451+
44364452
//---
44374453
// Two operand floating point data processing
44384454
//---
@@ -5308,7 +5324,7 @@ multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
53085324
[(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
53095325
}
53105326

5311-
// Supports only S and D element sizes, uses high bit of the size field
5327+
// Supports H, S and D element sizes, uses high bit of the size field
53125328
// as an extra opcode bit.
53135329
multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
53145330
SDPatternOperator OpNode> {
@@ -5331,6 +5347,25 @@ multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
53315347
[(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
53325348
}
53335349

5350+
// Supports only S and D element sizes
5351+
multiclass SIMDTwoVectorSD<bit U, bits<5> opc, string asm,
5352+
SDPatternOperator OpNode = null_frag> {
5353+
5354+
def v2f32 : BaseSIMDTwoSameVector<0, U, 00, opc, 0b00, V64,
5355+
asm, ".2s", ".2s",
5356+
[(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
5357+
def v4f32 : BaseSIMDTwoSameVector<1, U, 00, opc, 0b00, V128,
5358+
asm, ".4s", ".4s",
5359+
[(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
5360+
def v2f64 : BaseSIMDTwoSameVector<1, U, 01, opc, 0b00, V128,
5361+
asm, ".2d", ".2d",
5362+
[(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
5363+
}
5364+
5365+
multiclass FRIntNNTVector<bit U, bit op, string asm,
5366+
SDPatternOperator OpNode = null_frag> :
5367+
SIMDTwoVectorSD<U, {0b1111,op}, asm, OpNode>;
5368+
53345369
// Supports only S element size.
53355370
multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
53365371
SDPatternOperator OpNode> {

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

+17
Original file line numberDiff line numberDiff line change
@@ -64,6 +64,8 @@ def HasRCPC : Predicate<"Subtarget->hasRCPC()">,
6464
AssemblerPredicate<"FeatureRCPC", "rcpc">;
6565
def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">,
6666
AssemblerPredicate<"FeatureAltFPCmp", "altnzcv">;
67+
def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">,
68+
AssemblerPredicate<"FeatureFRInt3264", "frint3264">;
6769
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
6870
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
6971
def UseAlternateSExtLoadCVTF32
@@ -2939,6 +2941,13 @@ let SchedRW = [WriteFDiv] in {
29392941
defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
29402942
}
29412943

2944+
let Predicates = [HasFRInt3264] in {
2945+
defm FRINT32Z : FRIntNNT<0b00, "frint32z">;
2946+
defm FRINT64Z : FRIntNNT<0b10, "frint64z">;
2947+
defm FRINT32X : FRIntNNT<0b01, "frint32x">;
2948+
defm FRINT64X : FRIntNNT<0b11, "frint64x">;
2949+
} // HasFRInt3264
2950+
29422951
//===----------------------------------------------------------------------===//
29432952
// Floating point two operand instructions.
29442953
//===----------------------------------------------------------------------===//
@@ -3157,6 +3166,14 @@ defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
31573166
defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
31583167
defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
31593168
defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
3169+
3170+
let Predicates = [HasFRInt3264] in {
3171+
defm FRINT32Z : FRIntNNTVector<0, 0, "frint32z">;
3172+
defm FRINT64Z : FRIntNNTVector<0, 1, "frint64z">;
3173+
defm FRINT32X : FRIntNNTVector<1, 0, "frint32x">;
3174+
defm FRINT64X : FRIntNNTVector<1, 1, "frint64x">;
3175+
} // HasFRInt3264
3176+
31603177
defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
31613178
defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
31623179
defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",

‎llvm/lib/Target/AArch64/AArch64Subtarget.h

+2
Original file line numberDiff line numberDiff line change
@@ -96,6 +96,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
9696

9797
// Armv8.5-A Extensions
9898
bool HasAlternativeNZCV = false;
99+
bool HasFRInt3264 = false;
99100

100101
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
101102
bool HasZeroCycleRegMove = false;
@@ -310,6 +311,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
310311
bool hasRCPC() const { return HasRCPC; }
311312
bool hasAggressiveFMA() const { return HasAggressiveFMA; }
312313
bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
314+
bool hasFRInt3264() const { return HasFRInt3264; }
313315

314316
bool isLittleEndian() const { return IsLittle; }
315317

‎llvm/test/MC/AArch64/armv8.5a-frint-error.s

+52
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
2+
3+
// FP-to-int rounding, vector, illegal
4+
frint32z v0.4h, v0.4h
5+
frint32z v0.8b, v0.8b
6+
frint32z v0.8h, v0.8h
7+
frint32z v0.16b, v0.16b
8+
frint64z v0.4h, v0.4h
9+
frint64z v0.8b, v0.8b
10+
frint64z v0.8h, v0.8h
11+
frint64z v0.16b, v0.16b
12+
frint32x v0.4h, v0.4h
13+
frint32x v0.8b, v0.8b
14+
frint32x v0.8h, v0.8h
15+
frint32x v0.16b, v0.16b
16+
frint64x v0.4h, v0.4h
17+
frint64x v0.8b, v0.8b
18+
frint64x v0.8h, v0.8h
19+
frint64x v0.16b, v0.16b
20+
21+
// CHECK-ERROR: invalid operand for instruction
22+
// CHECK-ERROR-NEXT: frint32z v0.4h, v0.4h
23+
// CHECK-ERROR: invalid operand for instruction
24+
// CHECK-ERROR-NEXT: frint32z v0.8b, v0.8b
25+
// CHECK-ERROR: invalid operand for instruction
26+
// CHECK-ERROR-NEXT: frint32z v0.8h, v0.8h
27+
// CHECK-ERROR: invalid operand for instruction
28+
// CHECK-ERROR-NEXT: frint32z v0.16b, v0.16b
29+
// CHECK-ERROR: invalid operand for instruction
30+
// CHECK-ERROR-NEXT: frint64z v0.4h, v0.4h
31+
// CHECK-ERROR: invalid operand for instruction
32+
// CHECK-ERROR-NEXT: frint64z v0.8b, v0.8b
33+
// CHECK-ERROR: invalid operand for instruction
34+
// CHECK-ERROR-NEXT: frint64z v0.8h, v0.8h
35+
// CHECK-ERROR: invalid operand for instruction
36+
// CHECK-ERROR-NEXT: frint64z v0.16b, v0.16b
37+
// CHECK-ERROR: invalid operand for instruction
38+
// CHECK-ERROR-NEXT: frint32x v0.4h, v0.4h
39+
// CHECK-ERROR: invalid operand for instruction
40+
// CHECK-ERROR-NEXT: frint32x v0.8b, v0.8b
41+
// CHECK-ERROR: invalid operand for instruction
42+
// CHECK-ERROR-NEXT: frint32x v0.8h, v0.8h
43+
// CHECK-ERROR: invalid operand for instruction
44+
// CHECK-ERROR-NEXT: frint32x v0.16b, v0.16b
45+
// CHECK-ERROR: invalid operand for instruction
46+
// CHECK-ERROR-NEXT: frint64x v0.4h, v0.4h
47+
// CHECK-ERROR: invalid operand for instruction
48+
// CHECK-ERROR-NEXT: frint64x v0.8b, v0.8b
49+
// CHECK-ERROR: invalid operand for instruction
50+
// CHECK-ERROR-NEXT: frint64x v0.8h, v0.8h
51+
// CHECK-ERROR: invalid operand for instruction
52+
// CHECK-ERROR-NEXT: frint64x v0.16b, v0.16b

‎llvm/test/MC/AArch64/armv8.5a-frint.s

+92
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,92 @@
1+
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s
2+
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,+fptoint < %s | FileCheck %s
3+
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a,-v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOFRINT
4+
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOFRINT
5+
6+
// FP-to-int rounding, scalar
7+
frint32z s0, s1
8+
frint32z d0, d1
9+
frint64z s2, s3
10+
frint64z d2, d3
11+
frint32x s4, s5
12+
frint32x d4, d5
13+
frint64x s6, s7
14+
frint64x d6, d7
15+
16+
// CHECK: frint32z s0, s1 // encoding: [0x20,0x40,0x28,0x1e]
17+
// CHECK: frint32z d0, d1 // encoding: [0x20,0x40,0x68,0x1e]
18+
// CHECK: frint64z s2, s3 // encoding: [0x62,0x40,0x29,0x1e]
19+
// CHECK: frint64z d2, d3 // encoding: [0x62,0x40,0x69,0x1e]
20+
// CHECK: frint32x s4, s5 // encoding: [0xa4,0xc0,0x28,0x1e]
21+
// CHECK: frint32x d4, d5 // encoding: [0xa4,0xc0,0x68,0x1e]
22+
// CHECK: frint64x s6, s7 // encoding: [0xe6,0xc0,0x29,0x1e]
23+
// CHECK: frint64x d6, d7 // encoding: [0xe6,0xc0,0x69,0x1e]
24+
25+
// NOFRINT: instruction requires: frint3264
26+
// NOFRINT-NEXT: frint32z s0, s1
27+
// NOFRINT: instruction requires: frint3264
28+
// NOFRINT-NEXT: frint32z d0, d1
29+
// NOFRINT: instruction requires: frint3264
30+
// NOFRINT-NEXT: frint64z s2, s3
31+
// NOFRINT: instruction requires: frint3264
32+
// NOFRINT-NEXT: frint64z d2, d3
33+
// NOFRINT: instruction requires: frint3264
34+
// NOFRINT-NEXT: frint32x s4, s5
35+
// NOFRINT: instruction requires: frint3264
36+
// NOFRINT-NEXT: frint32x d4, d5
37+
// NOFRINT: instruction requires: frint3264
38+
// NOFRINT-NEXT: frint64x s6, s7
39+
// NOFRINT: instruction requires: frint3264
40+
// NOFRINT-NEXT: frint64x d6, d7
41+
42+
// FP-to-int rounding, vector
43+
frint32z v0.2s, v1.2s
44+
frint32z v0.2d, v1.2d
45+
frint32z v0.4s, v1.4s
46+
frint64z v2.2s, v3.2s
47+
frint64z v2.2d, v3.2d
48+
frint64z v2.4s, v3.4s
49+
frint32x v4.2s, v5.2s
50+
frint32x v4.2d, v5.2d
51+
frint32x v4.4s, v5.4s
52+
frint64x v6.2s, v7.2s
53+
frint64x v6.2d, v7.2d
54+
frint64x v6.4s, v7.4s
55+
56+
// CHECK: frint32z v0.2s, v1.2s // encoding: [0x20,0xe8,0x21,0x0e]
57+
// CHECK: frint32z v0.2d, v1.2d // encoding: [0x20,0xe8,0x61,0x4e]
58+
// CHECK: frint32z v0.4s, v1.4s // encoding: [0x20,0xe8,0x21,0x4e]
59+
// CHECK: frint64z v2.2s, v3.2s // encoding: [0x62,0xf8,0x21,0x0e]
60+
// CHECK: frint64z v2.2d, v3.2d // encoding: [0x62,0xf8,0x61,0x4e]
61+
// CHECK: frint64z v2.4s, v3.4s // encoding: [0x62,0xf8,0x21,0x4e]
62+
// CHECK: frint32x v4.2s, v5.2s // encoding: [0xa4,0xe8,0x21,0x2e]
63+
// CHECK: frint32x v4.2d, v5.2d // encoding: [0xa4,0xe8,0x61,0x6e]
64+
// CHECK: frint32x v4.4s, v5.4s // encoding: [0xa4,0xe8,0x21,0x6e]
65+
// CHECK: frint64x v6.2s, v7.2s // encoding: [0xe6,0xf8,0x21,0x2e]
66+
// CHECK: frint64x v6.2d, v7.2d // encoding: [0xe6,0xf8,0x61,0x6e]
67+
// CHECK: frint64x v6.4s, v7.4s // encoding: [0xe6,0xf8,0x21,0x6e]
68+
69+
// NOFRINT: instruction requires: frint3264
70+
// NOFRINT-NEXT: frint32z v0.2s, v1.2s
71+
// NOFRINT: instruction requires: frint3264
72+
// NOFRINT-NEXT: frint32z v0.2d, v1.2d
73+
// NOFRINT: instruction requires: frint3264
74+
// NOFRINT-NEXT: frint32z v0.4s, v1.4s
75+
// NOFRINT: instruction requires: frint3264
76+
// NOFRINT-NEXT: frint64z v2.2s, v3.2s
77+
// NOFRINT: instruction requires: frint3264
78+
// NOFRINT-NEXT: frint64z v2.2d, v3.2d
79+
// NOFRINT: instruction requires: frint3264
80+
// NOFRINT-NEXT: frint64z v2.4s, v3.4s
81+
// NOFRINT: instruction requires: frint3264
82+
// NOFRINT-NEXT: frint32x v4.2s, v5.2s
83+
// NOFRINT: instruction requires: frint3264
84+
// NOFRINT-NEXT: frint32x v4.2d, v5.2d
85+
// NOFRINT: instruction requires: frint3264
86+
// NOFRINT-NEXT: frint32x v4.4s, v5.4s
87+
// NOFRINT: instruction requires: frint3264
88+
// NOFRINT-NEXT: frint64x v6.2s, v7.2s
89+
// NOFRINT: instruction requires: frint3264
90+
// NOFRINT-NEXT: frint64x v6.2d, v7.2d
91+
// NOFRINT: instruction requires: frint3264
92+
// NOFRINT-NEXT: frint64x v6.4s, v7.4s

‎llvm/test/MC/Disassembler/AArch64/armv8.5a-dataproc.txt

+94-5
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,101 @@
11
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.5a --disassemble < %s | FileCheck %s
2-
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.5a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOV85
2+
# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.5a --disassemble < %s 2>%t | FileCheck %s --check-prefix=CHECK-NOV85
3+
# RUN: FileCheck %s --check-prefix=CHECK-NOV85-ERROR < %t
34

45
# Flag manipulation
56
[0x3f,0x40,0x00,0xd5]
67
[0x5f,0x40,0x00,0xd5]
78

8-
#CHECK: xaflag
9-
#CHECK: axflag
9+
# CHECK: xaflag
10+
# CHECK: axflag
1011

11-
#CHECK-NOV85: msr S0_0_C4_C0_1, xzr
12-
#CHECK-NOV85: msr S0_0_C4_C0_2, xzr
12+
# CHECK-NOV85: msr S0_0_C4_C0_1, xzr
13+
# CHECK-NOV85: msr S0_0_C4_C0_2, xzr
14+
15+
# FP-to-int rounding, scalar
16+
[0x20,0x40,0x28,0x1e]
17+
[0x20,0x40,0x68,0x1e]
18+
[0x62,0x40,0x29,0x1e]
19+
[0x62,0x40,0x69,0x1e]
20+
[0xa4,0xc0,0x28,0x1e]
21+
[0xa4,0xc0,0x68,0x1e]
22+
[0xe6,0xc0,0x29,0x1e]
23+
[0xe6,0xc0,0x69,0x1e]
24+
25+
# CHECK: frint32z s0, s1
26+
# CHECK: frint32z d0, d1
27+
# CHECK: frint64z s2, s3
28+
# CHECK: frint64z d2, d3
29+
# CHECK: frint32x s4, s5
30+
# CHECK: frint32x d4, d5
31+
# CHECK: frint64x s6, s7
32+
# CHECK: frint64x d6, d7
33+
34+
# CHECK-NOV85-ERROR: invalid instruction encoding
35+
# CHECK-NOV85-ERROR-NEXT: [0x20,0x40,0x28,0x1e]
36+
# CHECK-NOV85-ERROR: invalid instruction encoding
37+
# CHECK-NOV85-ERROR-NEXT: [0x20,0x40,0x68,0x1e]
38+
# CHECK-NOV85-ERROR: invalid instruction encoding
39+
# CHECK-NOV85-ERROR-NEXT: [0x62,0x40,0x29,0x1e]
40+
# CHECK-NOV85-ERROR: invalid instruction encoding
41+
# CHECK-NOV85-ERROR-NEXT: [0x62,0x40,0x69,0x1e]
42+
# CHECK-NOV85-ERROR: invalid instruction encoding
43+
# CHECK-NOV85-ERROR-NEXT: [0xa4,0xc0,0x28,0x1e]
44+
# CHECK-NOV85-ERROR: invalid instruction encoding
45+
# CHECK-NOV85-ERROR-NEXT: [0xa4,0xc0,0x68,0x1e]
46+
# CHECK-NOV85-ERROR: invalid instruction encoding
47+
# CHECK-NOV85-ERROR-NEXT: [0xe6,0xc0,0x29,0x1e]
48+
# CHECK-NOV85-ERROR: invalid instruction encoding
49+
# CHECK-NOV85-ERROR-NEXT: [0xe6,0xc0,0x69,0x1e]
50+
51+
# FP-to-int rounding, vector
52+
[0x20,0xe8,0x21,0x0e]
53+
[0x20,0xe8,0x61,0x4e]
54+
[0x20,0xe8,0x21,0x4e]
55+
[0x62,0xf8,0x21,0x0e]
56+
[0x62,0xf8,0x61,0x4e]
57+
[0x62,0xf8,0x21,0x4e]
58+
[0xa4,0xe8,0x21,0x2e]
59+
[0xa4,0xe8,0x61,0x6e]
60+
[0xa4,0xe8,0x21,0x6e]
61+
[0xe6,0xf8,0x21,0x2e]
62+
[0xe6,0xf8,0x61,0x6e]
63+
[0xe6,0xf8,0x21,0x6e]
64+
65+
#CHECK: frint32z v0.2s, v1.2s
66+
#CHECK: frint32z v0.2d, v1.2d
67+
#CHECK: frint32z v0.4s, v1.4s
68+
#CHECK: frint64z v2.2s, v3.2s
69+
#CHECK: frint64z v2.2d, v3.2d
70+
#CHECK: frint64z v2.4s, v3.4s
71+
#CHECK: frint32x v4.2s, v5.2s
72+
#CHECK: frint32x v4.2d, v5.2d
73+
#CHECK: frint32x v4.4s, v5.4s
74+
#CHECK: frint64x v6.2s, v7.2s
75+
#CHECK: frint64x v6.2d, v7.2d
76+
#CHECK: frint64x v6.4s, v7.4s
77+
78+
# CHECK-NOV85-ERROR: invalid instruction encoding
79+
# CHECK-NOV85-ERROR-NEXT: [0x20,0xe8,0x21,0x0e]
80+
# CHECK-NOV85-ERROR: invalid instruction encoding
81+
# CHECK-NOV85-ERROR-NEXT: [0x20,0xe8,0x61,0x4e]
82+
# CHECK-NOV85-ERROR: invalid instruction encoding
83+
# CHECK-NOV85-ERROR-NEXT: [0x20,0xe8,0x21,0x4e]
84+
# CHECK-NOV85-ERROR: invalid instruction encoding
85+
# CHECK-NOV85-ERROR-NEXT: [0x62,0xf8,0x21,0x0e]
86+
# CHECK-NOV85-ERROR: invalid instruction encoding
87+
# CHECK-NOV85-ERROR-NEXT: [0x62,0xf8,0x61,0x4e]
88+
# CHECK-NOV85-ERROR: invalid instruction encoding
89+
# CHECK-NOV85-ERROR-NEXT: [0x62,0xf8,0x21,0x4e]
90+
# CHECK-NOV85-ERROR: invalid instruction encoding
91+
# CHECK-NOV85-ERROR-NEXT: [0xa4,0xe8,0x21,0x2e]
92+
# CHECK-NOV85-ERROR: invalid instruction encoding
93+
# CHECK-NOV85-ERROR-NEXT: [0xa4,0xe8,0x61,0x6e]
94+
# CHECK-NOV85-ERROR: invalid instruction encoding
95+
# CHECK-NOV85-ERROR-NEXT: [0xa4,0xe8,0x21,0x6e]
96+
# CHECK-NOV85-ERROR: invalid instruction encoding
97+
# CHECK-NOV85-ERROR-NEXT: [0xe6,0xf8,0x21,0x2e]
98+
# CHECK-NOV85-ERROR: invalid instruction encoding
99+
# CHECK-NOV85-ERROR-NEXT: [0xe6,0xf8,0x61,0x6e]
100+
# CHECK-NOV85-ERROR: invalid instruction encoding
101+
# CHECK-NOV85-ERROR-NEXT: [0xe6,0xf8,0x21,0x6e]

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