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tlivelytlively
committedSep 20, 2018
[WebAssembly] Renumber SIMD ops
Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
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‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

+35-35
Original file line numberDiff line numberDiff line change
@@ -184,7 +184,7 @@ multiclass SIMDNot<ValueType vec_t, PatFrag splat_pat, ValueType lane_t> {
184184
(vec_t (splat_pat (lane_t -1)))
185185
))
186186
)],
187-
"v128.not\t$dst, $vec", "v128.not", 62>;
187+
"v128.not\t$dst, $vec", "v128.not", 63>;
188188
}
189189
multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec,
190190
string name, CondCode cond, bits<32> simdop> {
@@ -317,30 +317,30 @@ defm SHUFFLE_v16i8 :
317317

318318
let isCommutable = 1 in {
319319
defm ADD : SIMDBinaryInt<add, "add", 24>;
320-
defm ADD : SIMDBinaryFP<fadd, "add", 122>;
320+
defm ADD : SIMDBinaryFP<fadd, "add", 133>;
321321
defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 32>;
322-
defm MUL : SIMDBinaryFP<fmul, "mul", 128>;
322+
defm MUL : SIMDBinaryFP<fmul, "mul", 139>;
323323
} // isCommutable = 1
324324

325325
defm SUB : SIMDBinaryInt<sub, "sub", 28>;
326-
defm SUB : SIMDBinaryFP<fsub, "sub", 124>;
327-
defm DIV : SIMDBinaryFP<fdiv, "div", 126>;
326+
defm SUB : SIMDBinaryFP<fsub, "sub", 135>;
327+
defm DIV : SIMDBinaryFP<fdiv, "div", 137>;
328328

329-
defm "" : SIMDNegInt<v16i8, "i8x16", splat16, i32, 35>;
330-
defm "" : SIMDNegInt<v8i16, "i16x8", splat8, i32, 36>;
331-
defm "" : SIMDNegInt<v4i32, "i32x4", splat4, i32, 37>;
332-
defm "" : SIMDNegInt<v2i64, "i64x2", splat2, i64, 38>;
333-
defm "" : SIMDNegFP<v4f32, "f32x4", splat4, f32, 114>;
334-
defm "" : SIMDNegFP<v2f64, "f64x2", splat2, f64, 115>;
329+
defm "" : SIMDNegInt<v16i8, "i8x16", splat16, i32, 36>;
330+
defm "" : SIMDNegInt<v8i16, "i16x8", splat8, i32, 37>;
331+
defm "" : SIMDNegInt<v4i32, "i32x4", splat4, i32, 38>;
332+
defm "" : SIMDNegInt<v2i64, "i64x2", splat2, i64, 39>;
333+
defm "" : SIMDNegFP<v4f32, "f32x4", splat4, f32, 125>;
334+
defm "" : SIMDNegFP<v2f64, "f64x2", splat2, f64, 126>;
335335

336-
defm SHL : SIMDShiftInt<shl, "shl", 47, 0>;
337-
defm SHR_S : SIMDShiftInt<sra, "shr_s", 51, 1>;
338-
defm SHR_U : SIMDShiftInt<srl, "shr_u", 52, 1>;
336+
defm SHL : SIMDShiftInt<shl, "shl", 48, 0>;
337+
defm SHR_S : SIMDShiftInt<sra, "shr_s", 52, 1>;
338+
defm SHR_U : SIMDShiftInt<srl, "shr_u", 53, 1>;
339339

340340
let isCommutable = 1 in {
341-
defm AND : SIMDBitwise<and, "and", 59>;
342-
defm OR : SIMDBitwise<or, "or", 60>;
343-
defm XOR : SIMDBitwise<xor, "xor", 61>;
341+
defm AND : SIMDBitwise<and, "and", 60>;
342+
defm OR : SIMDBitwise<or, "or", 61>;
343+
defm XOR : SIMDBitwise<xor, "xor", 62>;
344344
} // isCommutable = 1
345345

346346
defm "" : SIMDNot<v16i8, splat16, i32>;
@@ -349,27 +349,27 @@ defm "" : SIMDNot<v4i32, splat4, i32>;
349349
defm "" : SIMDNot<v2i64, splat2, i64>;
350350

351351
let isCommutable = 1 in {
352-
defm EQ : SIMDConditionInt<"eq", SETEQ, 72>;
353-
defm EQ : SIMDConditionFP<"eq", SETOEQ, 75>;
354-
defm NE : SIMDConditionInt<"ne", SETNE, 77>;
355-
defm NE : SIMDConditionFP<"ne", SETUNE, 80>;
352+
defm EQ : SIMDConditionInt<"eq", SETEQ, 73>;
353+
defm EQ : SIMDConditionFP<"eq", SETOEQ, 77>;
354+
defm NE : SIMDConditionInt<"ne", SETNE, 79>;
355+
defm NE : SIMDConditionFP<"ne", SETUNE, 83>;
356356
} // isCommutable = 1
357357

358-
defm LT_S : SIMDConditionInt<"lt_s", SETLT, 82, 2>;
359-
defm LT_U : SIMDConditionInt<"lt_u", SETULT, 83, 2>;
360-
defm LT : SIMDConditionFP<"lt", SETOLT, 88>;
361-
defm LE_S : SIMDConditionInt<"le_s", SETLE, 90, 2>;
362-
defm LE_U : SIMDConditionInt<"le_u", SETULE, 91, 2>;
363-
defm LE : SIMDConditionFP<"le", SETOLE, 96>;
364-
defm GT_S : SIMDConditionInt<"gt_s", SETGT, 98, 2>;
365-
defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 99, 2>;
366-
defm GT : SIMDConditionFP<"gt", SETOGT, 104>;
367-
defm GE_S : SIMDConditionInt<"ge_s", SETGE, 106, 2>;
368-
defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 107, 2>;
369-
defm GE : SIMDConditionFP<"ge", SETOGE, 112>;
358+
defm LT_S : SIMDConditionInt<"lt_s", SETLT, 85, 2>;
359+
defm LT_U : SIMDConditionInt<"lt_u", SETULT, 86, 2>;
360+
defm LT : SIMDConditionFP<"lt", SETOLT, 93>;
361+
defm LE_S : SIMDConditionInt<"le_s", SETLE, 95, 2>;
362+
defm LE_U : SIMDConditionInt<"le_u", SETULE, 96, 2>;
363+
defm LE : SIMDConditionFP<"le", SETOLE, 103>;
364+
defm GT_S : SIMDConditionInt<"gt_s", SETGT, 105, 2>;
365+
defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 106, 2>;
366+
defm GT : SIMDConditionFP<"gt", SETOGT, 113>;
367+
defm GE_S : SIMDConditionInt<"ge_s", SETGE, 115, 2>;
368+
defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 116, 2>;
369+
defm GE : SIMDConditionFP<"ge", SETOGE, 123>;
370370

371-
defm "" : SIMDAbs<v4f32, "f32x4", 116>;
372-
defm "" : SIMDAbs<v2f64, "f64x2", 117>;
371+
defm "" : SIMDAbs<v4f32, "f32x4", 127>;
372+
defm "" : SIMDAbs<v2f64, "f64x2", 128>;
373373

374374
} // Defs = [ARGUMENTS]
375375

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