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jveselyjvesely
committedAug 7, 2018
AMDGPU: Remove broken i16 ternary patterns
Fixup test to check for GCN prefix These patterns always zero extend the result even though it might need sign extension. This has been broken since the addition of i16 support. It has popped up in mad_sat(char) test since min(max()) combination is turned into v_med3, resulting in the following (incorrect) sequence: v_mad_i16 v2, v10, v9, v11 v_med3_i32 v2, v2, v8, v7 Fixes mad_sat(char) piglit on VI. Differential Revision: https://reviews.llvm.org/D49836 llvm-svn: 339190
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Diff for: ‎llvm/lib/Target/AMDGPU/VOP3Instructions.td

-11
Original file line numberDiff line numberDiff line change
@@ -461,17 +461,6 @@ def : GCNPat <
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(inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
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>;
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464-
def : GCNPat<
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(i32 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))),
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(inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
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>;
468-
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def : GCNPat<
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(i64 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))),
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(REG_SEQUENCE VReg_64,
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(inst i16:$src0, i16:$src1, i16:$src2, (i1 0)), sub0,
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(V_MOV_B32_e32 (i32 0)), sub1)
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>;
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}
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477466
defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>;

Diff for: ‎llvm/test/CodeGen/AMDGPU/mad_uint24.ll

+90-3
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
3-
; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
4-
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC
5-
; RUN: llc < %s -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC
3+
; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC --check-prefix=GCN
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN
5+
; RUN: llc < %s -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=FUNC --check-prefix=GCN
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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@@ -138,3 +138,90 @@ bb18: ; preds = %bb4
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store i32 %tmp16, i32 addrspace(1)* %arg
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ret void
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}
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; FUNC-LABEL: {{^}}i8_mad_sat_16:
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; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
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; The result must be sign-extended
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; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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; EG: 8
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; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; GCN: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16
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; GCN: v_med3_i32 v{{[0-9]}}, [[EXT]],
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define amdgpu_kernel void @i8_mad_sat_16(i8 addrspace(1)* %out, i8 addrspace(1)* %in0, i8 addrspace(1)* %in1, i8 addrspace(1)* %in2, i64 addrspace(5)* %idx) {
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entry:
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%retval.0.i = load i64, i64 addrspace(5)* %idx
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%arrayidx = getelementptr inbounds i8, i8 addrspace(1)* %in0, i64 %retval.0.i
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%arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %in1, i64 %retval.0.i
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%arrayidx4 = getelementptr inbounds i8, i8 addrspace(1)* %in2, i64 %retval.0.i
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%l1 = load i8, i8 addrspace(1)* %arrayidx, align 1
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%l2 = load i8, i8 addrspace(1)* %arrayidx2, align 1
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%l3 = load i8, i8 addrspace(1)* %arrayidx4, align 1
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%conv1.i = sext i8 %l1 to i16
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%conv3.i = sext i8 %l2 to i16
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%conv5.i = sext i8 %l3 to i16
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%mul.i.i.i = mul nsw i16 %conv3.i, %conv1.i
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%add.i.i = add i16 %mul.i.i.i, %conv5.i
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%c4 = icmp sgt i16 %add.i.i, -128
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%cond.i.i = select i1 %c4, i16 %add.i.i, i16 -128
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%c5 = icmp slt i16 %cond.i.i, 127
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%cond13.i.i = select i1 %c5, i16 %cond.i.i, i16 127
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%conv8.i = trunc i16 %cond13.i.i to i8
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%arrayidx7 = getelementptr inbounds i8, i8 addrspace(1)* %out, i64 %retval.0.i
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store i8 %conv8.i, i8 addrspace(1)* %arrayidx7, align 1
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ret void
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}
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; FUNC-LABEL: {{^}}i8_mad_32:
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; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
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; The result must be sign-extended
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; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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; EG: 8
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; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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; GCN: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16
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define amdgpu_kernel void @i8_mad_32(i32 addrspace(1)* %out, i8 addrspace(1)* %a, i8 addrspace(1)* %b, i8 addrspace(1)* %c, i64 addrspace(5)* %idx) {
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entry:
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%retval.0.i = load i64, i64 addrspace(5)* %idx
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%arrayidx = getelementptr inbounds i8, i8 addrspace(1)* %a, i64 %retval.0.i
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%arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %b, i64 %retval.0.i
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%arrayidx4 = getelementptr inbounds i8, i8 addrspace(1)* %c, i64 %retval.0.i
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%la = load i8, i8 addrspace(1)* %arrayidx, align 1
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%lb = load i8, i8 addrspace(1)* %arrayidx2, align 1
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%lc = load i8, i8 addrspace(1)* %arrayidx4, align 1
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%exta = sext i8 %la to i16
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%extb = sext i8 %lb to i16
194+
%extc = sext i8 %lc to i16
195+
%mul = mul i16 %exta, %extb
196+
%mad = add i16 %mul, %extc
197+
%mad_ext = sext i16 %mad to i32
198+
store i32 %mad_ext, i32 addrspace(1)* %out
199+
ret void
200+
}
201+
202+
; FUNC-LABEL: {{^}}i8_mad_64:
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; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
204+
; The result must be sign-extended
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; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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; EG: 8
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; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
208+
; VI: v_mad_u16 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
209+
; GCN: v_bfe_i32 [[EXT:v[0-9]]], [[MAD]], 0, 16
210+
define amdgpu_kernel void @i8_mad_64(i64 addrspace(1)* %out, i8 addrspace(1)* %a, i8 addrspace(1)* %b, i8 addrspace(1)* %c, i64 addrspace(5)* %idx) {
211+
entry:
212+
%retval.0.i = load i64, i64 addrspace(5)* %idx
213+
%arrayidx = getelementptr inbounds i8, i8 addrspace(1)* %a, i64 %retval.0.i
214+
%arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %b, i64 %retval.0.i
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%arrayidx4 = getelementptr inbounds i8, i8 addrspace(1)* %c, i64 %retval.0.i
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%la = load i8, i8 addrspace(1)* %arrayidx, align 1
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%lb = load i8, i8 addrspace(1)* %arrayidx2, align 1
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%lc = load i8, i8 addrspace(1)* %arrayidx4, align 1
219+
%exta = sext i8 %la to i16
220+
%extb = sext i8 %lb to i16
221+
%extc = sext i8 %lc to i16
222+
%mul = mul i16 %exta, %extb
223+
%mad = add i16 %mul, %extc
224+
%mad_ext = sext i16 %mad to i64
225+
store i64 %mad_ext, i64 addrspace(1)* %out
226+
ret void
227+
}

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