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Commit 41fa858

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committedJul 13, 2018
[X86][SLH] Add VEX and EVEX conversion instructions to isDataInvariantLoad
-Drop the intrinsic versions of conversion instructions. These should be handled when we do vectors. They shouldn't show up in scalar code. -Add the float<->double conversions which were missing. -Add the AVX512 and AVX version of the conversion instructions including the unsigned integer conversions unique to AVX512 Differential Revision: https://reviews.llvm.org/D49313 llvm-svn: 337066
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‎llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

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Original file line numberDiff line numberDiff line change
@@ -938,19 +938,25 @@ static bool isDataInvariantLoad(MachineInstr &MI) {
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case X86::SHRX64rm:
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// Conversions are believed to be constant time and don't set flags.
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// FIXME: Add AVX versions.
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case X86::CVTSD2SI64rm_Int:
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case X86::CVTSD2SIrm_Int:
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case X86::CVTSS2SI64rm_Int:
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case X86::CVTSS2SIrm_Int:
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case X86::CVTTSD2SI64rm:
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case X86::CVTTSD2SI64rm_Int:
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case X86::CVTTSD2SIrm:
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case X86::CVTTSD2SIrm_Int:
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case X86::CVTTSS2SI64rm:
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case X86::CVTTSS2SI64rm_Int:
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case X86::CVTTSS2SIrm:
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case X86::CVTTSS2SIrm_Int:
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case X86::CVTTSD2SI64rm: case X86::VCVTTSD2SI64rm: case X86::VCVTTSD2SI64Zrm:
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case X86::CVTTSD2SIrm: case X86::VCVTTSD2SIrm: case X86::VCVTTSD2SIZrm:
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case X86::CVTTSS2SI64rm: case X86::VCVTTSS2SI64rm: case X86::VCVTTSS2SI64Zrm:
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case X86::CVTTSS2SIrm: case X86::VCVTTSS2SIrm: case X86::VCVTTSS2SIZrm:
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case X86::CVTSI2SDrm: case X86::VCVTSI2SDrm: case X86::VCVTSI2SDZrm:
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case X86::CVTSI2SSrm: case X86::VCVTSI2SSrm: case X86::VCVTSI2SSZrm:
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case X86::CVTSI642SDrm: case X86::VCVTSI642SDrm: case X86::VCVTSI642SDZrm:
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case X86::CVTSI642SSrm: case X86::VCVTSI642SSrm: case X86::VCVTSI642SSZrm:
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case X86::CVTSS2SDrm: case X86::VCVTSS2SDrm: case X86::VCVTSS2SDZrm:
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case X86::CVTSD2SSrm: case X86::VCVTSD2SSrm: case X86::VCVTSD2SSZrm:
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// AVX512 added unsigned integer conversions.
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case X86::VCVTTSD2USI64Zrm:
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case X86::VCVTTSD2USIZrm:
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case X86::VCVTTSS2USI64Zrm:
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case X86::VCVTTSS2USIZrm:
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case X86::VCVTUSI2SDZrm:
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case X86::VCVTUSI642SDZrm:
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case X86::VCVTUSI2SSZrm:
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case X86::VCVTUSI642SSZrm:
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// Loads to register don't set flags.
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case X86::MOV8rm:

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