Skip to content

Commit 0f111dd

Browse files
author
Simon Dardis
committedJun 20, 2018
[mips] Add microMIPS specific addressing patterns.
These are identical but use microMIPS instructions instead of MIPS instructions. Also, flatten the 'let AdditionalPredicates = [InMicroMips]' by using the ISA_MICROMIPS adjective. Add tests for constant materialization. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48275 llvm-svn: 335185
1 parent d1d83df commit 0f111dd

File tree

4 files changed

+187
-91
lines changed

4 files changed

+187
-91
lines changed
 

‎llvm/lib/Target/Mips/MicroMipsInstrInfo.td

+87-66
Original file line numberDiff line numberDiff line change
@@ -1165,75 +1165,96 @@ let DecoderNamespace = "MicroMips" in {
11651165
// MicroMips arbitrary patterns that map to one or more instructions
11661166
//===----------------------------------------------------------------------===//
11671167

1168-
let AdditionalPredicates = [InMicroMips] in {
1169-
def : MipsPat<(i32 immLi16:$imm),
1170-
(LI16_MM immLi16:$imm)>;
1171-
1172-
defm : MaterializeImms<i32, ZERO, ADDiu_MM, LUi_MM, ORi_MM>;
1173-
}
1174-
1175-
let Predicates = [InMicroMips] in {
1176-
def : MipsPat<(not GPRMM16:$in),
1177-
(NOT16_MM GPRMM16:$in)>;
1178-
def : MipsPat<(not GPR32:$in),
1179-
(NOR_MM GPR32Opnd:$in, ZERO)>;
1180-
1181-
def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
1182-
(ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>;
1183-
def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
1184-
(ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
1185-
def : MipsPat<(add GPR32:$src, immSExt16:$imm),
1186-
(ADDiu_MM GPR32:$src, immSExt16:$imm)>;
1187-
1188-
def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1189-
(ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
1190-
def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1191-
(ANDi_MM GPR32:$src, immZExt16:$imm)>;
1192-
1193-
def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
1194-
(SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
1195-
def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
1196-
(SLL_MM GPR32:$src, immZExt5:$imm)>;
1197-
def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs),
1198-
(SLLV_MM GPR32:$lhs, GPR32:$rhs)>;
1199-
1200-
def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
1201-
(SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
1202-
def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
1203-
(SRL_MM GPR32:$src, immZExt5:$imm)>;
1204-
def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs),
1205-
(SRLV_MM GPR32:$lhs, GPR32:$rhs)>;
1206-
1207-
def : MipsPat<(sra GPR32:$src, immZExt5:$imm),
1208-
(SRA_MM GPR32:$src, immZExt5:$imm)>;
1209-
def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs),
1210-
(SRAV_MM GPR32:$lhs, GPR32:$rhs)>;
1211-
1212-
def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1213-
(SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
1214-
def : MipsPat<(store GPR32:$src, addr:$addr),
1215-
(SW_MM GPR32:$src, addr:$addr)>;
1216-
1217-
def : MipsPat<(load addrimm4lsl2:$addr),
1218-
(LW16_MM addrimm4lsl2:$addr)>;
1219-
def : MipsPat<(load addr:$addr),
1220-
(LW_MM addr:$addr)>;
1221-
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1222-
(SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
1223-
1224-
def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_MM addr:$src)>,
1225-
ISA_MICROMIPS;
1168+
defm : MipsHiLoRelocs<LUi_MM, ADDiu_MM, ZERO, GPR32Opnd>, ISA_MICROMIPS;
12261169

1227-
def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_MM addr:$src)>,
1228-
ISA_MICROMIPS;
1170+
def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi_MM tglobaladdr:$in)>,
1171+
ISA_MICROMIPS;
1172+
def : MipsPat<(MipsGotHi texternalsym:$in), (LUi_MM texternalsym:$in)>,
1173+
ISA_MICROMIPS;
12291174

1230-
def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_MM addr:$src)>,
1231-
ISA_MICROMIPS;
1175+
// gp_rel relocs
1176+
def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1177+
(ADDiu_MM GPR32:$gp, tglobaladdr:$in)>, ISA_MICROMIPS;
1178+
def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1179+
(ADDiu_MM GPR32:$gp, tconstpool:$in)>, ISA_MICROMIPS;
1180+
1181+
def : WrapperPat<tglobaladdr, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1182+
def : WrapperPat<tconstpool, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1183+
def : WrapperPat<texternalsym, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1184+
def : WrapperPat<tblockaddress, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1185+
def : WrapperPat<tjumptable, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1186+
def : WrapperPat<tglobaltlsaddr, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1187+
1188+
def : MipsPat<(atomic_load_8 addr:$a), (LB_MM addr:$a)>, ISA_MICROMIPS;
1189+
def : MipsPat<(atomic_load_16 addr:$a), (LH_MM addr:$a)>, ISA_MICROMIPS;
1190+
def : MipsPat<(atomic_load_32 addr:$a), (LW_MM addr:$a)>, ISA_MICROMIPS;
1191+
1192+
def : MipsPat<(i32 immLi16:$imm),
1193+
(LI16_MM immLi16:$imm)>, ISA_MICROMIPS;
1194+
1195+
defm : MaterializeImms<i32, ZERO, ADDiu_MM, LUi_MM, ORi_MM>, ISA_MICROMIPS;
1196+
1197+
def : MipsPat<(not GPRMM16:$in),
1198+
(NOT16_MM GPRMM16:$in)>, ISA_MICROMIPS;
1199+
def : MipsPat<(not GPR32:$in),
1200+
(NOR_MM GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS;
1201+
1202+
def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
1203+
(ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>, ISA_MICROMIPS;
1204+
def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
1205+
(ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>, ISA_MICROMIPS;
1206+
def : MipsPat<(add GPR32:$src, immSExt16:$imm),
1207+
(ADDiu_MM GPR32:$src, immSExt16:$imm)>, ISA_MICROMIPS;
1208+
1209+
def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1210+
(ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>, ISA_MICROMIPS;
1211+
def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1212+
(ANDi_MM GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS;
1213+
1214+
def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
1215+
(SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>, ISA_MICROMIPS;
1216+
def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
1217+
(SLL_MM GPR32:$src, immZExt5:$imm)>, ISA_MICROMIPS;
1218+
def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs),
1219+
(SLLV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1220+
1221+
def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
1222+
(SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>, ISA_MICROMIPS;
1223+
def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
1224+
(SRL_MM GPR32:$src, immZExt5:$imm)>, ISA_MICROMIPS;
1225+
def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs),
1226+
(SRLV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1227+
1228+
def : MipsPat<(sra GPR32:$src, immZExt5:$imm),
1229+
(SRA_MM GPR32:$src, immZExt5:$imm)>, ISA_MICROMIPS;
1230+
def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs),
1231+
(SRAV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1232+
1233+
def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1234+
(SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS;
1235+
def : MipsPat<(store GPR32:$src, addr:$addr),
1236+
(SW_MM GPR32:$src, addr:$addr)>, ISA_MICROMIPS;
1237+
1238+
def : MipsPat<(load addrimm4lsl2:$addr),
1239+
(LW16_MM addrimm4lsl2:$addr)>, ISA_MICROMIPS;
1240+
def : MipsPat<(load addr:$addr),
1241+
(LW_MM addr:$addr)>, ISA_MICROMIPS;
1242+
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1243+
(SUBu_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1244+
1245+
def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_MM addr:$src)>,
1246+
ISA_MICROMIPS;
1247+
1248+
def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_MM addr:$src)>,
1249+
ISA_MICROMIPS;
1250+
1251+
def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_MM addr:$src)>,
1252+
ISA_MICROMIPS;
1253+
1254+
let AddedComplexity = 40 in
1255+
def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
1256+
(LH_MM addrRegImm:$a)>, ISA_MICROMIPS;
12321257

1233-
let AddedComplexity = 40 in
1234-
def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
1235-
(LH_MM addrRegImm:$a)>, ISA_MICROMIPS;
1236-
}
12371258

12381259
def : MipsPat<(bswap GPR32:$rt), (ROTR_MM (WSBH_MM GPR32:$rt), 16)>,
12391260
ISA_MICROMIPS;

‎llvm/lib/Target/Mips/MipsInstrInfo.td

+26-25
Original file line numberDiff line numberDiff line change
@@ -3016,33 +3016,34 @@ multiclass MipsHiLoRelocs<Instruction Lui, Instruction Addiu,
30163016
(Addiu GPROpnd:$hi, tglobaltlsaddr:$lo)>;
30173017
}
30183018

3019-
defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>;
3020-
3021-
def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
3022-
def : MipsPat<(MipsGotHi texternalsym:$in), (LUi texternalsym:$in)>;
3023-
3024-
// gp_rel relocs
3025-
def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
3026-
(ADDiu GPR32:$gp, tglobaladdr:$in)>, ABI_NOT_N64;
3027-
def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
3028-
(ADDiu GPR32:$gp, tconstpool:$in)>, ABI_NOT_N64;
3029-
3030-
// wrapper_pic
3031-
class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
3032-
MipsPat<(MipsWrapper RC:$gp, node:$in),
3033-
(ADDiuOp RC:$gp, node:$in)>;
3019+
let AdditionalPredicates = [NotInMicroMips] in {
3020+
defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>, ISA_MIPS1;
30343021

3035-
def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
3036-
def : WrapperPat<tconstpool, ADDiu, GPR32>;
3037-
def : WrapperPat<texternalsym, ADDiu, GPR32>;
3038-
def : WrapperPat<tblockaddress, ADDiu, GPR32>;
3039-
def : WrapperPat<tjumptable, ADDiu, GPR32>;
3040-
def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
3022+
def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi tglobaladdr:$in)>, ISA_MIPS1;
3023+
def : MipsPat<(MipsGotHi texternalsym:$in), (LUi texternalsym:$in)>,
3024+
ISA_MIPS1;
30413025

3042-
let AdditionalPredicates = [NotInMicroMips] in {
3043-
// Mips does not have "not", so we expand our way
3044-
def : MipsPat<(not GPR32:$in),
3045-
(NOR GPR32Opnd:$in, ZERO)>;
3026+
// gp_rel relocs
3027+
def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
3028+
(ADDiu GPR32:$gp, tglobaladdr:$in)>, ISA_MIPS1, ABI_NOT_N64;
3029+
def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
3030+
(ADDiu GPR32:$gp, tconstpool:$in)>, ISA_MIPS1, ABI_NOT_N64;
3031+
3032+
// wrapper_pic
3033+
class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
3034+
MipsPat<(MipsWrapper RC:$gp, node:$in),
3035+
(ADDiuOp RC:$gp, node:$in)>;
3036+
3037+
def : WrapperPat<tglobaladdr, ADDiu, GPR32>, ISA_MIPS1;
3038+
def : WrapperPat<tconstpool, ADDiu, GPR32>, ISA_MIPS1;
3039+
def : WrapperPat<texternalsym, ADDiu, GPR32>, ISA_MIPS1;
3040+
def : WrapperPat<tblockaddress, ADDiu, GPR32>, ISA_MIPS1;
3041+
def : WrapperPat<tjumptable, ADDiu, GPR32>, ISA_MIPS1;
3042+
def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>, ISA_MIPS1;
3043+
3044+
// Mips does not have "not", so we expand our way
3045+
def : MipsPat<(not GPR32:$in),
3046+
(NOR GPR32Opnd:$in, ZERO)>, ISA_MIPS1;
30463047
}
30473048

30483049
// extended loads
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
1+
; RUN: llc -march=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS
2+
; RUN: llc -march=mips -relocation-model=pic -mxgot < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS-XGOT
3+
4+
; RUN: llc -march=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM
5+
; RUN: llc -march=mips -relocation-model=pic -mxgot -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM-XGOT
6+
7+
; REQUIRES: asserts
8+
9+
; Tests that the correct ISA is selected for computing a global address.
10+
11+
@x = global i32 0
12+
@a = global i32 1
13+
declare i32 @y(i32*, i32)
14+
15+
define i32 @z() {
16+
entry:
17+
%0 = load i32, i32* @a, align 4
18+
%1 = call i32 @y(i32 * @x, i32 %0)
19+
ret i32 %1
20+
}
21+
22+
; MIPS-LABEL: ===== Instruction selection ends:
23+
; MIPS: t[[A:[0-9]+]]: i32 = LUi TargetGlobalAddress:i32<i32* @x> 0 [TF=4]
24+
; MIPS: t{{.*}}: i32 = ADDiu t[[A]], TargetGlobalAddress:i32<i32* @x> 0 [TF=5]
25+
26+
; MIPS-XGOT-LABEL: ===== Instruction selection ends:
27+
; MIPS-XGOT: t[[B:[0-9]+]]: i32 = LUi TargetGlobalAddress:i32<i32* @x> 0 [TF=20]
28+
; MIPS-XGOT: t[[C:[0-9]+]]: i32 = ADDu t[[B]], Register:i32 %0
29+
; MIPS-XGOT: t{{.*}}: i32,ch = LW<Mem:(load 4 from got)> t[[C]], TargetGlobalAddress:i32<i32* @x> 0 [TF=21], t{{.*}}
30+
31+
; MM-LABEL: ===== Instruction selection ends:
32+
; MM: t[[A:[0-9]+]]: i32 = LUi_MM TargetGlobalAddress:i32<i32* @x> 0 [TF=4]
33+
; MM: t{{.*}}: i32 = ADDiu_MM t[[A]], TargetGlobalAddress:i32<i32* @x> 0 [TF=5]
34+
35+
; MM-XGOT-LABEL: ===== Instruction selection ends:
36+
; MM-XGOT: t[[B:[0-9]+]]: i32 = LUi_MM TargetGlobalAddress:i32<i32* @x> 0 [TF=20]
37+
; MM-XGOT: t[[C:[0-9]+]]: i32 = ADDU16_MM t[[B]], Register:i32 %0
38+
; MM-XGOT: t{{.*}}: i32,ch = LW_MM<Mem:(load 4 from got)> t[[C]], TargetGlobalAddress:i32<i32* @x> 0 [TF=21], t0
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
; RUN: llc -march=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS
2+
; RUN: llc -march=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM
3+
4+
; REQUIRES: asserts
5+
6+
; Test that the correct ISA is selected for the materialization of constants.
7+
8+
; The four parameters are picked to use these instructions: li16, addiu, lui,
9+
; lui+addiu.
10+
11+
declare void @e(i32)
12+
declare void @f(i32, i32, i32)
13+
define void @g() {
14+
entry:
15+
call void @f (i32 1, i32 2048, i32 8388608)
16+
call void @e (i32 150994946)
17+
ret void
18+
}
19+
20+
; MIPS-LABEL: ===== Instruction selection ends:
21+
; MIPS-DAG: t{{[0-9]+}}: i32 = ADDiu Register:i32 $zero, TargetConstant:i32<1>
22+
; MIPS-DAG: t{{[0-9]+}}: i32 = ADDiu Register:i32 $zero, TargetConstant:i32<2048>
23+
; MIPS-DAG: t{{[0-9]+}}: i32 = LUi TargetConstant:i32<128>
24+
; MIPS: t{{[0-9]+}}: ch,glue = JAL TargetGlobalAddress:i32<void (i32, i32, i32)* @f>
25+
26+
; MIPS: t[[A:[0-9]+]]: i32 = LUi TargetConstant:i32<2304>
27+
; MIPS: t{{[0-9]+}}: i32 = ORi t[[A]], TargetConstant:i32<2>
28+
29+
; MM-LABEL: ===== Instruction selection ends:
30+
; MM-DAG: t{{[0-9]+}}: i32 = LI16_MM TargetConstant:i32<1>
31+
; MM-DAG: t{{[0-9]+}}: i32 = ADDiu_MM Register:i32 $zero, TargetConstant:i32<2048>
32+
; MM-DAG: t{{[0-9]+}}: i32 = LUi_MM TargetConstant:i32<128>
33+
; MM: t{{[0-9]+}}: ch,glue = JAL_MM TargetGlobalAddress:i32<void (i32, i32, i32)* @f>
34+
35+
; MM: t[[A:[0-9]+]]: i32 = LUi_MM TargetConstant:i32<2304>
36+
; MM: t{{[0-9]+}}: i32 = ORi_MM t[[A]], TargetConstant:i32<2>

0 commit comments

Comments
 (0)
Please sign in to comment.