Skip to content

Commit c2696d5

Browse files
topperctopperc
committedJun 20, 2018
[X86] Use setcc ISD opcode for AVX512 integer comparisons all the way to isel
I don't believe there is any real reason to have separate X86 specific opcodes for vector compares. Setcc has the same behavior just uses a different encoding for the condition code. I had to change the CondCodeAction for SETLT and SETLE to prevent some transforms from changing SETGT lowering. Differential Revision: https://reviews.llvm.org/D43608 llvm-svn: 335173
·
llvmorg-21-initllvmorg-7.0.0-rc1
1 parent 11b0275 commit c2696d5

9 files changed

+273
-182
lines changed
 

‎llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -470,7 +470,7 @@ namespace {
470470
// type.
471471
static bool isLegalMaskCompare(SDNode *N, const X86Subtarget *Subtarget) {
472472
unsigned Opcode = N->getOpcode();
473-
if (Opcode == X86ISD::CMPM || Opcode == X86ISD::CMPMU ||
473+
if (Opcode == X86ISD::CMPM || Opcode == ISD::SETCC ||
474474
Opcode == X86ISD::CMPM_RND || Opcode == X86ISD::VFPCLASS) {
475475
// We can get 256-bit 8 element types here without VLX being enabled. When
476476
// this happens we will use 512-bit operations and the mask will not be

‎llvm/lib/Target/X86/X86ISelLowering.cpp

+45-51
Original file line numberDiff line numberDiff line change
@@ -814,6 +814,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
814814
setOperationAction(ISD::SETCC, VT, Custom);
815815
setOperationAction(ISD::CTPOP, VT, Custom);
816816
setOperationAction(ISD::CTTZ, VT, Custom);
817+
818+
// The condition codes aren't legal in SSE/AVX and under AVX512 we use
819+
// setcc all the way to isel and prefer SETGT in some isel patterns.
820+
setCondCodeAction(ISD::SETLT, VT, Custom);
821+
setCondCodeAction(ISD::SETLE, VT, Custom);
817822
}
818823

819824
for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
@@ -1056,6 +1061,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
10561061
setOperationAction(ISD::CTPOP, VT, Custom);
10571062
setOperationAction(ISD::CTTZ, VT, Custom);
10581063
setOperationAction(ISD::CTLZ, VT, Custom);
1064+
1065+
// The condition codes aren't legal in SSE/AVX and under AVX512 we use
1066+
// setcc all the way to isel and prefer SETGT in some isel patterns.
1067+
setCondCodeAction(ISD::SETLT, VT, Custom);
1068+
setCondCodeAction(ISD::SETLE, VT, Custom);
10591069
}
10601070

10611071
if (Subtarget.hasAnyFMA()) {
@@ -1338,6 +1348,12 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
13381348
setOperationAction(ISD::CTTZ, VT, Custom);
13391349
setOperationAction(ISD::ROTL, VT, Custom);
13401350
setOperationAction(ISD::ROTR, VT, Custom);
1351+
setOperationAction(ISD::SETCC, VT, Custom);
1352+
1353+
// The condition codes aren't legal in SSE/AVX and under AVX512 we use
1354+
// setcc all the way to isel and prefer SETGT in some isel patterns.
1355+
setCondCodeAction(ISD::SETLT, VT, Custom);
1356+
setCondCodeAction(ISD::SETLE, VT, Custom);
13411357
}
13421358

13431359
// Need to promote to 64-bit even though we have 32-bit masked instructions
@@ -1551,6 +1567,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
15511567
setOperationAction(ISD::UMAX, VT, Legal);
15521568
setOperationAction(ISD::SMIN, VT, Legal);
15531569
setOperationAction(ISD::UMIN, VT, Legal);
1570+
setOperationAction(ISD::SETCC, VT, Custom);
15541571

15551572
setOperationPromotedToType(ISD::AND, VT, MVT::v8i64);
15561573
setOperationPromotedToType(ISD::OR, VT, MVT::v8i64);
@@ -5180,8 +5197,8 @@ static bool isMaskedZeroUpperBitsvXi1(unsigned int Opcode) {
51805197
default:
51815198
return false;
51825199
case X86ISD::CMPM:
5183-
case X86ISD::CMPMU:
51845200
case X86ISD::CMPM_RND:
5201+
case ISD::SETCC:
51855202
return true;
51865203
}
51875204
}
@@ -6978,17 +6995,13 @@ static SDValue lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp,
69786995
BOperand = ZeroExtended.getOperand(0);
69796996
else
69806997
BOperand = Ld.getOperand(0).getOperand(0);
6981-
if (BOperand.getValueType().isVector() &&
6982-
BOperand.getSimpleValueType().getVectorElementType() == MVT::i1) {
6983-
if ((EltType == MVT::i64 && (VT.getVectorElementType() == MVT::i8 ||
6984-
NumElts == 8)) || // for broadcastmb2q
6985-
(EltType == MVT::i32 && (VT.getVectorElementType() == MVT::i16 ||
6986-
NumElts == 16))) { // for broadcastmw2d
6987-
SDValue Brdcst =
6988-
DAG.getNode(X86ISD::VBROADCASTM, dl,
6989-
MVT::getVectorVT(EltType, NumElts), BOperand);
6990-
return DAG.getBitcast(VT, Brdcst);
6991-
}
6998+
MVT MaskVT = BOperand.getSimpleValueType();
6999+
if ((EltType == MVT::i64 && MaskVT == MVT::v8i1) || // for broadcastmb2q
7000+
(EltType == MVT::i32 && MaskVT == MVT::v16i1)) { // for broadcastmw2d
7001+
SDValue Brdcst =
7002+
DAG.getNode(X86ISD::VBROADCASTM, dl,
7003+
MVT::getVectorVT(EltType, NumElts), BOperand);
7004+
return DAG.getBitcast(VT, Brdcst);
69927005
}
69937006
}
69947007
}
@@ -14757,8 +14770,8 @@ static SDValue lower1BitVectorShuffle(const SDLoc &DL, ArrayRef<int> Mask,
1475714770
int NumElems = VT.getVectorNumElements();
1475814771
if ((Subtarget.hasBWI() && (NumElems >= 32)) ||
1475914772
(Subtarget.hasDQI() && (NumElems < 32)))
14760-
return DAG.getNode(X86ISD::CMPM, DL, VT, DAG.getConstant(0, DL, ExtVT),
14761-
Shuffle, DAG.getConstant(6, DL, MVT::i8));
14773+
return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, ExtVT),
14774+
Shuffle, ISD::SETGT);
1476214775

1476314776
return DAG.getNode(ISD::TRUNCATE, DL, VT, Shuffle);
1476414777
}
@@ -14996,9 +15009,9 @@ SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
1499615009
"Should have a size-matched integer condition!");
1499715010
// Build a mask by testing the condition against zero.
1499815011
MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
14999-
SDValue Mask = DAG.getNode(X86ISD::CMPM, dl, MaskVT, Cond,
15000-
getZeroVector(VT, Subtarget, DAG, dl),
15001-
DAG.getConstant(4, dl, MVT::i8));
15012+
SDValue Mask = DAG.getSetCC(dl, MaskVT, Cond,
15013+
getZeroVector(VT, Subtarget, DAG, dl),
15014+
ISD::SETNE);
1500215015
// Now return a new VSELECT using the mask.
1500315016
return DAG.getSelect(dl, VT, Mask, Op.getOperand(1), Op.getOperand(2));
1500415017
}
@@ -16962,8 +16975,8 @@ static SDValue LowerTruncateVecI1(SDValue Op, SelectionDAG &DAG,
1696216975
DAG.getConstant(ShiftInx, DL, ExtVT));
1696316976
In = DAG.getBitcast(InVT, In);
1696416977
}
16965-
return DAG.getNode(X86ISD::CMPM, DL, VT, DAG.getConstant(0, DL, InVT),
16966-
In, DAG.getConstant(6, DL, MVT::i8));
16978+
return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, InVT),
16979+
In, ISD::SETGT);
1696716980
}
1696816981
// Use TESTD/Q, extended vector to packed dword/qword.
1696916982
assert((InVT.is256BitVector() || InVT.is128BitVector()) &&
@@ -17010,11 +17023,10 @@ static SDValue LowerTruncateVecI1(SDValue Op, SelectionDAG &DAG,
1701017023
}
1701117024
// If we have DQI, emit a pattern that will be iseled as vpmovq2m/vpmovd2m.
1701217025
if (Subtarget.hasDQI())
17013-
return DAG.getNode(X86ISD::CMPM, DL, VT, DAG.getConstant(0, DL, InVT),
17014-
In, DAG.getConstant(6, DL, MVT::i8));
17015-
return DAG.getNode(X86ISD::CMPM, DL, VT, In,
17016-
getZeroVector(InVT, Subtarget, DAG, DL),
17017-
DAG.getConstant(4, DL, MVT::i8));
17026+
return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, InVT),
17027+
In, ISD::SETGT);
17028+
return DAG.getSetCC(DL, VT, In, getZeroVector(InVT, Subtarget, DAG, DL),
17029+
ISD::SETNE);
1701817030
}
1701917031

1702017032
SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
@@ -18091,28 +18103,13 @@ static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
1809118103
ISD::isBuildVectorAllZeros(Op0.getNode()))
1809218104
std::swap(Op0, Op1);
1809318105

18094-
bool Swap = false;
18095-
unsigned SSECC;
18096-
switch (SetCCOpcode) {
18097-
default: llvm_unreachable("Unexpected SETCC condition");
18098-
case ISD::SETNE: SSECC = 4; break;
18099-
case ISD::SETEQ: SSECC = 0; break;
18100-
case ISD::SETULT: SSECC = 1; break;
18101-
case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH;
18102-
case ISD::SETUGT:
18103-
case ISD::SETGT: SSECC = 6; break;
18104-
case ISD::SETUGE:
18105-
case ISD::SETGE: SSECC = 5; break;
18106-
case ISD::SETULE:
18107-
case ISD::SETLE: SSECC = 2; break;
18108-
}
18109-
if (Swap)
18106+
// Prefer SETGT over SETLT.
18107+
if (SetCCOpcode == ISD::SETLT) {
18108+
SetCCOpcode = ISD::getSetCCSwappedOperands(SetCCOpcode);
1811018109
std::swap(Op0, Op1);
18110+
}
1811118111

18112-
unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode) ? X86ISD::CMPMU
18113-
: X86ISD::CMPM;
18114-
return DAG.getNode(Opc, dl, VT, Op0, Op1,
18115-
DAG.getConstant(SSECC, dl, MVT::i8));
18112+
return DAG.getSetCC(dl, VT, Op0, Op1, SetCCOpcode);
1811618113
}
1811718114

1811818115
/// Try to turn a VSETULT into a VSETULE by modifying its second
@@ -20167,7 +20164,6 @@ static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
2016720164
default: break;
2016820165
case X86ISD::CMPM:
2016920166
case X86ISD::CMPM_RND:
20170-
case X86ISD::CMPMU:
2017120167
case X86ISD::VPSHUFBITQMB:
2017220168
case X86ISD::VFPCLASS:
2017320169
return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
@@ -22978,8 +22974,8 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
2297822974
SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
2297922975
if (VT.is512BitVector()) {
2298022976
assert(VT == MVT::v64i8 && "Unexpected element type!");
22981-
SDValue CMP = DAG.getNode(X86ISD::CMPM, dl, MVT::v64i1, Zeros, R,
22982-
DAG.getConstant(6, dl, MVT::i8));
22977+
SDValue CMP = DAG.getSetCC(dl, MVT::v64i1, Zeros, R,
22978+
ISD::SETGT);
2298322979
return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, CMP);
2298422980
}
2298522981
return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
@@ -23499,9 +23495,8 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
2349923495
V0 = DAG.getBitcast(VT, V0);
2350023496
V1 = DAG.getBitcast(VT, V1);
2350123497
Sel = DAG.getBitcast(VT, Sel);
23502-
Sel = DAG.getNode(X86ISD::CMPM, dl, MaskVT,
23503-
DAG.getConstant(0, dl, VT), Sel,
23504-
DAG.getConstant(6, dl, MVT::i8));
23498+
Sel = DAG.getSetCC(dl, MaskVT, DAG.getConstant(0, dl, VT), Sel,
23499+
ISD::SETGT);
2350523500
return DAG.getBitcast(SelVT, DAG.getSelect(dl, VT, Sel, V0, V1));
2350623501
} else if (Subtarget.hasSSE41()) {
2350723502
// On SSE41 targets we make use of the fact that VSELECT lowers
@@ -25716,7 +25711,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
2571625711
case X86ISD::COMI: return "X86ISD::COMI";
2571725712
case X86ISD::UCOMI: return "X86ISD::UCOMI";
2571825713
case X86ISD::CMPM: return "X86ISD::CMPM";
25719-
case X86ISD::CMPMU: return "X86ISD::CMPMU";
2572025714
case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
2572125715
case X86ISD::SETCC: return "X86ISD::SETCC";
2572225716
case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";

‎llvm/lib/Target/X86/X86ISelLowering.h

-1
Original file line numberDiff line numberDiff line change
@@ -345,7 +345,6 @@ namespace llvm {
345345
/// Vector comparison generating mask bits for fp and
346346
/// integer signed and unsigned data types.
347347
CMPM,
348-
CMPMU,
349348
// Vector comparison with rounding mode for FP values
350349
CMPM_RND,
351350

0 commit comments

Comments
 (0)
Please sign in to comment.