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[AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) ins…
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…tructions.

Summary:
The variants added by this patch are:
- SQINC  (signed increment)
- UQINC  (unsigned increment)
- SQDEC  (signed decrement)
- UQDEC  (unsigned decrement)

For example:
  uqincw  x0, all, mul #4

Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar

Differential Revision: https://reviews.llvm.org/D47715

llvm-svn: 334948
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sdesmalen-arm committed Jun 18, 2018
1 parent 9173c97 commit 13684d8
Showing 34 changed files with 4,484 additions and 0 deletions.
20 changes: 20 additions & 0 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
Original file line number Diff line number Diff line change
@@ -527,6 +527,26 @@ let Predicates = [HasSVE] in {
defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">;
defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">;

defm SQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00100, "sqincb">;
defm UQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00101, "uqincb">;
defm SQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00110, "sqdecb">;
defm UQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00111, "uqdecb">;

defm SQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01100, "sqinch">;
defm UQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01101, "uqinch">;
defm SQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01110, "sqdech">;
defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech">;

defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw">;
defm UQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10101, "uqincw">;
defm SQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10110, "sqdecw">;
defm UQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10111, "uqdecw">;

defm SQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11100, "sqincd">;
defm UQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11101, "uqincd">;
defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">;
defm UQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11111, "uqdecd">;

defm INDEX_RR : sve_int_index_rr<"index">;
defm INDEX_IR : sve_int_index_ir<"index">;
defm INDEX_RI : sve_int_index_ri<"index">;
31 changes: 31 additions & 0 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
Original file line number Diff line number Diff line change
@@ -314,6 +314,37 @@ multiclass sve_int_pred_pattern_a<bits<3> opc, string asm> {
(!cast<Instruction>(NAME) GPR64:$Rdn, 0b11111, 1), 2>;
}

class sve_int_pred_pattern_b<bits<5> opc, string asm, RegisterOperand dt,
RegisterOperand st>
: I<(outs dt:$Rdn), (ins st:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
asm, "\t$Rdn, $pattern, mul $imm4",
"",
[]>, Sched<[]> {
bits<5> Rdn;
bits<5> pattern;
bits<4> imm4;
let Inst{31-24} = 0b00000100;
let Inst{23-22} = opc{4-3};
let Inst{21} = 0b1;
let Inst{20} = opc{2};
let Inst{19-16} = imm4;
let Inst{15-12} = 0b1111;
let Inst{11-10} = opc{1-0};
let Inst{9-5} = pattern;
let Inst{4-0} = Rdn;

let Constraints = "$Rdn = $_Rdn";
}

multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm> {
def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>;

def : InstAlias<asm # "\t$Rdn, $pattern",
(!cast<Instruction>(NAME) GPR64z:$Rdn, sve_pred_enum:$pattern, 1), 1>;
def : InstAlias<asm # "\t$Rdn",
(!cast<Instruction>(NAME) GPR64z:$Rdn, 0b11111, 1), 2>;
}


//===----------------------------------------------------------------------===//
// SVE Permute - Cross Lane Group
62 changes: 62 additions & 0 deletions llvm/test/MC/AArch64/SVE/sqdecb-diagnostics.s
Original file line number Diff line number Diff line change
@@ -0,0 +1,62 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s

// ------------------------------------------------------------------------- //
// Invalid result register

sqdecb w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

sqdecb wsp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb wsp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

sqdecb sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sqdecb sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:


// ------------------------------------------------------------------------- //
// Immediate not compatible with encode/decode function.

sqdecb x0, all, mul #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqdecb x0, all, mul #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

sqdecb x0, all, mul #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqdecb x0, all, mul #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

sqdecb x0, all, mul #17
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
// CHECK-NEXT: sqdecb x0, all, mul #17
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:


// ------------------------------------------------------------------------- //
// Invalid predicate patterns

sqdecb x0, vl512
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqdecb x0, vl512
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

sqdecb x0, vl9
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqdecb x0, vl9
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

sqdecb x0, #-1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqdecb x0, #-1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

sqdecb x0, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
// CHECK-NEXT: sqdecb x0, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
215 changes: 215 additions & 0 deletions llvm/test/MC/AArch64/SVE/sqdecb.s
Original file line number Diff line number Diff line change
@@ -0,0 +1,215 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN

// ---------------------------------------------------------------------------//
// Test 64-bit form (x0) and its aliases
// ---------------------------------------------------------------------------//

sqdecb x0
// CHECK-INST: sqdecb x0
// CHECK-ENCODING: [0xe0,0xfb,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 fb 30 04 <unknown>

sqdecb x0, all
// CHECK-INST: sqdecb x0
// CHECK-ENCODING: [0xe0,0xfb,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 fb 30 04 <unknown>

sqdecb x0, all, mul #1
// CHECK-INST: sqdecb x0
// CHECK-ENCODING: [0xe0,0xfb,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 fb 30 04 <unknown>

sqdecb x0, all, mul #16
// CHECK-INST: sqdecb x0, all, mul #16
// CHECK-ENCODING: [0xe0,0xfb,0x3f,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 fb 3f 04 <unknown>


// ---------------------------------------------------------------------------//
// Test all patterns for 64-bit form
// ---------------------------------------------------------------------------//

sqdecb x0, pow2
// CHECK-INST: sqdecb x0, pow2
// CHECK-ENCODING: [0x00,0xf8,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 f8 30 04 <unknown>

sqdecb x0, vl1
// CHECK-INST: sqdecb x0, vl1
// CHECK-ENCODING: [0x20,0xf8,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f8 30 04 <unknown>

sqdecb x0, vl2
// CHECK-INST: sqdecb x0, vl2
// CHECK-ENCODING: [0x40,0xf8,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 40 f8 30 04 <unknown>

sqdecb x0, vl3
// CHECK-INST: sqdecb x0, vl3
// CHECK-ENCODING: [0x60,0xf8,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 f8 30 04 <unknown>

sqdecb x0, vl4
// CHECK-INST: sqdecb x0, vl4
// CHECK-ENCODING: [0x80,0xf8,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 f8 30 04 <unknown>

sqdecb x0, vl5
// CHECK-INST: sqdecb x0, vl5
// CHECK-ENCODING: [0xa0,0xf8,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 f8 30 04 <unknown>

sqdecb x0, vl6
// CHECK-INST: sqdecb x0, vl6
// CHECK-ENCODING: [0xc0,0xf8,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c0 f8 30 04 <unknown>

sqdecb x0, vl7
// CHECK-INST: sqdecb x0, vl7
// CHECK-ENCODING: [0xe0,0xf8,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 f8 30 04 <unknown>

sqdecb x0, vl8
// CHECK-INST: sqdecb x0, vl8
// CHECK-ENCODING: [0x00,0xf9,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 f9 30 04 <unknown>

sqdecb x0, vl16
// CHECK-INST: sqdecb x0, vl16
// CHECK-ENCODING: [0x20,0xf9,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 f9 30 04 <unknown>

sqdecb x0, vl32
// CHECK-INST: sqdecb x0, vl32
// CHECK-ENCODING: [0x40,0xf9,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 40 f9 30 04 <unknown>

sqdecb x0, vl64
// CHECK-INST: sqdecb x0, vl64
// CHECK-ENCODING: [0x60,0xf9,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 f9 30 04 <unknown>

sqdecb x0, vl128
// CHECK-INST: sqdecb x0, vl128
// CHECK-ENCODING: [0x80,0xf9,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 f9 30 04 <unknown>

sqdecb x0, vl256
// CHECK-INST: sqdecb x0, vl256
// CHECK-ENCODING: [0xa0,0xf9,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 f9 30 04 <unknown>

sqdecb x0, #14
// CHECK-INST: sqdecb x0, #14
// CHECK-ENCODING: [0xc0,0xf9,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c0 f9 30 04 <unknown>

sqdecb x0, #15
// CHECK-INST: sqdecb x0, #15
// CHECK-ENCODING: [0xe0,0xf9,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 f9 30 04 <unknown>

sqdecb x0, #16
// CHECK-INST: sqdecb x0, #16
// CHECK-ENCODING: [0x00,0xfa,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 fa 30 04 <unknown>

sqdecb x0, #17
// CHECK-INST: sqdecb x0, #17
// CHECK-ENCODING: [0x20,0xfa,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 fa 30 04 <unknown>

sqdecb x0, #18
// CHECK-INST: sqdecb x0, #18
// CHECK-ENCODING: [0x40,0xfa,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 40 fa 30 04 <unknown>

sqdecb x0, #19
// CHECK-INST: sqdecb x0, #19
// CHECK-ENCODING: [0x60,0xfa,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 fa 30 04 <unknown>

sqdecb x0, #20
// CHECK-INST: sqdecb x0, #20
// CHECK-ENCODING: [0x80,0xfa,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 fa 30 04 <unknown>

sqdecb x0, #21
// CHECK-INST: sqdecb x0, #21
// CHECK-ENCODING: [0xa0,0xfa,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 fa 30 04 <unknown>

sqdecb x0, #22
// CHECK-INST: sqdecb x0, #22
// CHECK-ENCODING: [0xc0,0xfa,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c0 fa 30 04 <unknown>

sqdecb x0, #23
// CHECK-INST: sqdecb x0, #23
// CHECK-ENCODING: [0xe0,0xfa,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: e0 fa 30 04 <unknown>

sqdecb x0, #24
// CHECK-INST: sqdecb x0, #24
// CHECK-ENCODING: [0x00,0xfb,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 fb 30 04 <unknown>

sqdecb x0, #25
// CHECK-INST: sqdecb x0, #25
// CHECK-ENCODING: [0x20,0xfb,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 20 fb 30 04 <unknown>

sqdecb x0, #26
// CHECK-INST: sqdecb x0, #26
// CHECK-ENCODING: [0x40,0xfb,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 40 fb 30 04 <unknown>

sqdecb x0, #27
// CHECK-INST: sqdecb x0, #27
// CHECK-ENCODING: [0x60,0xfb,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 60 fb 30 04 <unknown>

sqdecb x0, #28
// CHECK-INST: sqdecb x0, #28
// CHECK-ENCODING: [0x80,0xfb,0x30,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 80 fb 30 04 <unknown>
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