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[AArch64][SVE] Asm: Support for saturating INC/DEC (64bit scalar) ins…
…tructions. Summary: The variants added by this patch are: - SQINC (signed increment) - UQINC (unsigned increment) - SQDEC (signed decrement) - UQDEC (unsigned decrement) For example: uqincw x0, all, mul #4 Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar Differential Revision: https://reviews.llvm.org/D47715 llvm-svn: 334948
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s | ||
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// ------------------------------------------------------------------------- // | ||
// Invalid result register | ||
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sqdecb w0 | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand | ||
// CHECK-NEXT: sqdecb w0 | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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sqdecb wsp | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand | ||
// CHECK-NEXT: sqdecb wsp | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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sqdecb sp | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand | ||
// CHECK-NEXT: sqdecb sp | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// ------------------------------------------------------------------------- // | ||
// Immediate not compatible with encode/decode function. | ||
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sqdecb x0, all, mul #-1 | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] | ||
// CHECK-NEXT: sqdecb x0, all, mul #-1 | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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sqdecb x0, all, mul #0 | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] | ||
// CHECK-NEXT: sqdecb x0, all, mul #0 | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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sqdecb x0, all, mul #17 | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] | ||
// CHECK-NEXT: sqdecb x0, all, mul #17 | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// ------------------------------------------------------------------------- // | ||
// Invalid predicate patterns | ||
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sqdecb x0, vl512 | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern | ||
// CHECK-NEXT: sqdecb x0, vl512 | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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sqdecb x0, vl9 | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern | ||
// CHECK-NEXT: sqdecb x0, vl9 | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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sqdecb x0, #-1 | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern | ||
// CHECK-NEXT: sqdecb x0, #-1 | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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sqdecb x0, #32 | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern | ||
// CHECK-NEXT: sqdecb x0, #32 | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ | ||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ | ||
// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ | ||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN | ||
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// ---------------------------------------------------------------------------// | ||
// Test 64-bit form (x0) and its aliases | ||
// ---------------------------------------------------------------------------// | ||
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sqdecb x0 | ||
// CHECK-INST: sqdecb x0 | ||
// CHECK-ENCODING: [0xe0,0xfb,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: e0 fb 30 04 <unknown> | ||
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sqdecb x0, all | ||
// CHECK-INST: sqdecb x0 | ||
// CHECK-ENCODING: [0xe0,0xfb,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: e0 fb 30 04 <unknown> | ||
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sqdecb x0, all, mul #1 | ||
// CHECK-INST: sqdecb x0 | ||
// CHECK-ENCODING: [0xe0,0xfb,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: e0 fb 30 04 <unknown> | ||
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sqdecb x0, all, mul #16 | ||
// CHECK-INST: sqdecb x0, all, mul #16 | ||
// CHECK-ENCODING: [0xe0,0xfb,0x3f,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: e0 fb 3f 04 <unknown> | ||
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// ---------------------------------------------------------------------------// | ||
// Test all patterns for 64-bit form | ||
// ---------------------------------------------------------------------------// | ||
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sqdecb x0, pow2 | ||
// CHECK-INST: sqdecb x0, pow2 | ||
// CHECK-ENCODING: [0x00,0xf8,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 00 f8 30 04 <unknown> | ||
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sqdecb x0, vl1 | ||
// CHECK-INST: sqdecb x0, vl1 | ||
// CHECK-ENCODING: [0x20,0xf8,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 20 f8 30 04 <unknown> | ||
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sqdecb x0, vl2 | ||
// CHECK-INST: sqdecb x0, vl2 | ||
// CHECK-ENCODING: [0x40,0xf8,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 40 f8 30 04 <unknown> | ||
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sqdecb x0, vl3 | ||
// CHECK-INST: sqdecb x0, vl3 | ||
// CHECK-ENCODING: [0x60,0xf8,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 60 f8 30 04 <unknown> | ||
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sqdecb x0, vl4 | ||
// CHECK-INST: sqdecb x0, vl4 | ||
// CHECK-ENCODING: [0x80,0xf8,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 80 f8 30 04 <unknown> | ||
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sqdecb x0, vl5 | ||
// CHECK-INST: sqdecb x0, vl5 | ||
// CHECK-ENCODING: [0xa0,0xf8,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: a0 f8 30 04 <unknown> | ||
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sqdecb x0, vl6 | ||
// CHECK-INST: sqdecb x0, vl6 | ||
// CHECK-ENCODING: [0xc0,0xf8,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: c0 f8 30 04 <unknown> | ||
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sqdecb x0, vl7 | ||
// CHECK-INST: sqdecb x0, vl7 | ||
// CHECK-ENCODING: [0xe0,0xf8,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: e0 f8 30 04 <unknown> | ||
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sqdecb x0, vl8 | ||
// CHECK-INST: sqdecb x0, vl8 | ||
// CHECK-ENCODING: [0x00,0xf9,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 00 f9 30 04 <unknown> | ||
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sqdecb x0, vl16 | ||
// CHECK-INST: sqdecb x0, vl16 | ||
// CHECK-ENCODING: [0x20,0xf9,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 20 f9 30 04 <unknown> | ||
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sqdecb x0, vl32 | ||
// CHECK-INST: sqdecb x0, vl32 | ||
// CHECK-ENCODING: [0x40,0xf9,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 40 f9 30 04 <unknown> | ||
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sqdecb x0, vl64 | ||
// CHECK-INST: sqdecb x0, vl64 | ||
// CHECK-ENCODING: [0x60,0xf9,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 60 f9 30 04 <unknown> | ||
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sqdecb x0, vl128 | ||
// CHECK-INST: sqdecb x0, vl128 | ||
// CHECK-ENCODING: [0x80,0xf9,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 80 f9 30 04 <unknown> | ||
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sqdecb x0, vl256 | ||
// CHECK-INST: sqdecb x0, vl256 | ||
// CHECK-ENCODING: [0xa0,0xf9,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: a0 f9 30 04 <unknown> | ||
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sqdecb x0, #14 | ||
// CHECK-INST: sqdecb x0, #14 | ||
// CHECK-ENCODING: [0xc0,0xf9,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: c0 f9 30 04 <unknown> | ||
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sqdecb x0, #15 | ||
// CHECK-INST: sqdecb x0, #15 | ||
// CHECK-ENCODING: [0xe0,0xf9,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: e0 f9 30 04 <unknown> | ||
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sqdecb x0, #16 | ||
// CHECK-INST: sqdecb x0, #16 | ||
// CHECK-ENCODING: [0x00,0xfa,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 00 fa 30 04 <unknown> | ||
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sqdecb x0, #17 | ||
// CHECK-INST: sqdecb x0, #17 | ||
// CHECK-ENCODING: [0x20,0xfa,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 20 fa 30 04 <unknown> | ||
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sqdecb x0, #18 | ||
// CHECK-INST: sqdecb x0, #18 | ||
// CHECK-ENCODING: [0x40,0xfa,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 40 fa 30 04 <unknown> | ||
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sqdecb x0, #19 | ||
// CHECK-INST: sqdecb x0, #19 | ||
// CHECK-ENCODING: [0x60,0xfa,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 60 fa 30 04 <unknown> | ||
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sqdecb x0, #20 | ||
// CHECK-INST: sqdecb x0, #20 | ||
// CHECK-ENCODING: [0x80,0xfa,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 80 fa 30 04 <unknown> | ||
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sqdecb x0, #21 | ||
// CHECK-INST: sqdecb x0, #21 | ||
// CHECK-ENCODING: [0xa0,0xfa,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: a0 fa 30 04 <unknown> | ||
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sqdecb x0, #22 | ||
// CHECK-INST: sqdecb x0, #22 | ||
// CHECK-ENCODING: [0xc0,0xfa,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: c0 fa 30 04 <unknown> | ||
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sqdecb x0, #23 | ||
// CHECK-INST: sqdecb x0, #23 | ||
// CHECK-ENCODING: [0xe0,0xfa,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: e0 fa 30 04 <unknown> | ||
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sqdecb x0, #24 | ||
// CHECK-INST: sqdecb x0, #24 | ||
// CHECK-ENCODING: [0x00,0xfb,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 00 fb 30 04 <unknown> | ||
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sqdecb x0, #25 | ||
// CHECK-INST: sqdecb x0, #25 | ||
// CHECK-ENCODING: [0x20,0xfb,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 20 fb 30 04 <unknown> | ||
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sqdecb x0, #26 | ||
// CHECK-INST: sqdecb x0, #26 | ||
// CHECK-ENCODING: [0x40,0xfb,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 40 fb 30 04 <unknown> | ||
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sqdecb x0, #27 | ||
// CHECK-INST: sqdecb x0, #27 | ||
// CHECK-ENCODING: [0x60,0xfb,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 60 fb 30 04 <unknown> | ||
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sqdecb x0, #28 | ||
// CHECK-INST: sqdecb x0, #28 | ||
// CHECK-ENCODING: [0x80,0xfb,0x30,0x04] | ||
// CHECK-ERROR: instruction requires: sve | ||
// CHECK-UNKNOWN: 80 fb 30 04 <unknown> |
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