|
| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py |
| 2 | +; RUN: opt < %s -instcombine -S | FileCheck %s |
| 3 | + |
| 4 | +; https://bugs.llvm.org/show_bug.cgi?id=37603 |
| 5 | + |
| 6 | +; Pattern: |
| 7 | +; (1 << NBits) - 1 |
| 8 | +; Should be transformed into: |
| 9 | +; ~(-(1 << NBits)) |
| 10 | +; The `not` may end up being folded into `and` |
| 11 | + |
| 12 | +; ============================================================================ ; |
| 13 | +; Most basic positive tests |
| 14 | +; ============================================================================ ; |
| 15 | + |
| 16 | +; No no-wrap tags on shl |
| 17 | + |
| 18 | +define i32 @shl_add(i32 %NBits) { |
| 19 | +; CHECK-LABEL: @shl_add( |
| 20 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]] |
| 21 | +; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], -1 |
| 22 | +; CHECK-NEXT: ret i32 [[RET]] |
| 23 | +; |
| 24 | + %setbit = shl i32 1, %NBits |
| 25 | + %ret = add i32 %setbit, -1 |
| 26 | + ret i32 %ret |
| 27 | +} |
| 28 | + |
| 29 | +define i32 @shl_add_nsw(i32 %NBits) { |
| 30 | +; CHECK-LABEL: @shl_add_nsw( |
| 31 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]] |
| 32 | +; CHECK-NEXT: [[RET:%.*]] = add nsw i32 [[SETBIT]], -1 |
| 33 | +; CHECK-NEXT: ret i32 [[RET]] |
| 34 | +; |
| 35 | + %setbit = shl i32 1, %NBits |
| 36 | + %ret = add nsw i32 %setbit, -1 |
| 37 | + ret i32 %ret |
| 38 | +} |
| 39 | + |
| 40 | +define i32 @shl_add_nuw(i32 %NBits) { |
| 41 | +; CHECK-LABEL: @shl_add_nuw( |
| 42 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]] |
| 43 | +; CHECK-NEXT: [[RET:%.*]] = add nuw i32 [[SETBIT]], -1 |
| 44 | +; CHECK-NEXT: ret i32 [[RET]] |
| 45 | +; |
| 46 | + %setbit = shl i32 1, %NBits |
| 47 | + %ret = add nuw i32 %setbit, -1 |
| 48 | + ret i32 %ret |
| 49 | +} |
| 50 | + |
| 51 | +define i32 @shl_add_nsw_nuw(i32 %NBits) { |
| 52 | +; CHECK-LABEL: @shl_add_nsw_nuw( |
| 53 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]] |
| 54 | +; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[SETBIT]], -1 |
| 55 | +; CHECK-NEXT: ret i32 [[RET]] |
| 56 | +; |
| 57 | + %setbit = shl i32 1, %NBits |
| 58 | + %ret = add nuw nsw i32 %setbit, -1 |
| 59 | + ret i32 %ret |
| 60 | +} |
| 61 | + |
| 62 | +; shl is nsw |
| 63 | + |
| 64 | +define i32 @shl_nsw_add(i32 %NBits) { |
| 65 | +; CHECK-LABEL: @shl_nsw_add( |
| 66 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl nsw i32 1, [[NBITS:%.*]] |
| 67 | +; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], -1 |
| 68 | +; CHECK-NEXT: ret i32 [[RET]] |
| 69 | +; |
| 70 | + %setbit = shl nsw i32 1, %NBits |
| 71 | + %ret = add i32 %setbit, -1 |
| 72 | + ret i32 %ret |
| 73 | +} |
| 74 | + |
| 75 | +define i32 @shl_nsw_add_nsw(i32 %NBits) { |
| 76 | +; CHECK-LABEL: @shl_nsw_add_nsw( |
| 77 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl nsw i32 1, [[NBITS:%.*]] |
| 78 | +; CHECK-NEXT: [[RET:%.*]] = add nsw i32 [[SETBIT]], -1 |
| 79 | +; CHECK-NEXT: ret i32 [[RET]] |
| 80 | +; |
| 81 | + %setbit = shl nsw i32 1, %NBits |
| 82 | + %ret = add nsw i32 %setbit, -1 |
| 83 | + ret i32 %ret |
| 84 | +} |
| 85 | + |
| 86 | +define i32 @shl_nsw_add_nuw(i32 %NBits) { |
| 87 | +; CHECK-LABEL: @shl_nsw_add_nuw( |
| 88 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl nsw i32 1, [[NBITS:%.*]] |
| 89 | +; CHECK-NEXT: [[RET:%.*]] = add nuw i32 [[SETBIT]], -1 |
| 90 | +; CHECK-NEXT: ret i32 [[RET]] |
| 91 | +; |
| 92 | + %setbit = shl nsw i32 1, %NBits |
| 93 | + %ret = add nuw i32 %setbit, -1 |
| 94 | + ret i32 %ret |
| 95 | +} |
| 96 | + |
| 97 | +define i32 @shl_nsw_add_nsw_nuw(i32 %NBits) { |
| 98 | +; CHECK-LABEL: @shl_nsw_add_nsw_nuw( |
| 99 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl nsw i32 1, [[NBITS:%.*]] |
| 100 | +; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[SETBIT]], -1 |
| 101 | +; CHECK-NEXT: ret i32 [[RET]] |
| 102 | +; |
| 103 | + %setbit = shl nsw i32 1, %NBits |
| 104 | + %ret = add nuw nsw i32 %setbit, -1 |
| 105 | + ret i32 %ret |
| 106 | +} |
| 107 | + |
| 108 | +; shl is nuw |
| 109 | + |
| 110 | +define i32 @shl_nuw_add(i32 %NBits) { |
| 111 | +; CHECK-LABEL: @shl_nuw_add( |
| 112 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl nuw i32 1, [[NBITS:%.*]] |
| 113 | +; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], -1 |
| 114 | +; CHECK-NEXT: ret i32 [[RET]] |
| 115 | +; |
| 116 | + %setbit = shl nuw i32 1, %NBits |
| 117 | + %ret = add i32 %setbit, -1 |
| 118 | + ret i32 %ret |
| 119 | +} |
| 120 | + |
| 121 | +define i32 @shl_nuw_add_nsw(i32 %NBits) { |
| 122 | +; CHECK-LABEL: @shl_nuw_add_nsw( |
| 123 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl nuw i32 1, [[NBITS:%.*]] |
| 124 | +; CHECK-NEXT: [[RET:%.*]] = add nsw i32 [[SETBIT]], -1 |
| 125 | +; CHECK-NEXT: ret i32 [[RET]] |
| 126 | +; |
| 127 | + %setbit = shl nuw i32 1, %NBits |
| 128 | + %ret = add nsw i32 %setbit, -1 |
| 129 | + ret i32 %ret |
| 130 | +} |
| 131 | + |
| 132 | +define i32 @shl_nuw_add_nuw(i32 %NBits) { |
| 133 | +; CHECK-LABEL: @shl_nuw_add_nuw( |
| 134 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl nuw i32 1, [[NBITS:%.*]] |
| 135 | +; CHECK-NEXT: [[RET:%.*]] = add nuw i32 [[SETBIT]], -1 |
| 136 | +; CHECK-NEXT: ret i32 [[RET]] |
| 137 | +; |
| 138 | + %setbit = shl nuw i32 1, %NBits |
| 139 | + %ret = add nuw i32 %setbit, -1 |
| 140 | + ret i32 %ret |
| 141 | +} |
| 142 | + |
| 143 | +define i32 @shl_nuw_add_nsw_nuw(i32 %NBits) { |
| 144 | +; CHECK-LABEL: @shl_nuw_add_nsw_nuw( |
| 145 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl nuw i32 1, [[NBITS:%.*]] |
| 146 | +; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[SETBIT]], -1 |
| 147 | +; CHECK-NEXT: ret i32 [[RET]] |
| 148 | +; |
| 149 | + %setbit = shl nuw i32 1, %NBits |
| 150 | + %ret = add nuw nsw i32 %setbit, -1 |
| 151 | + ret i32 %ret |
| 152 | +} |
| 153 | + |
| 154 | +; shl is nuw nsw |
| 155 | + |
| 156 | +define i32 @shl_nsw_nuw_add(i32 %NBits) { |
| 157 | +; CHECK-LABEL: @shl_nsw_nuw_add( |
| 158 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl nuw nsw i32 1, [[NBITS:%.*]] |
| 159 | +; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], -1 |
| 160 | +; CHECK-NEXT: ret i32 [[RET]] |
| 161 | +; |
| 162 | + %setbit = shl nuw nsw i32 1, %NBits |
| 163 | + %ret = add i32 %setbit, -1 |
| 164 | + ret i32 %ret |
| 165 | +} |
| 166 | + |
| 167 | +define i32 @shl_nsw_nuw_add_nsw(i32 %NBits) { |
| 168 | +; CHECK-LABEL: @shl_nsw_nuw_add_nsw( |
| 169 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl nuw nsw i32 1, [[NBITS:%.*]] |
| 170 | +; CHECK-NEXT: [[RET:%.*]] = add nsw i32 [[SETBIT]], -1 |
| 171 | +; CHECK-NEXT: ret i32 [[RET]] |
| 172 | +; |
| 173 | + %setbit = shl nuw nsw i32 1, %NBits |
| 174 | + %ret = add nsw i32 %setbit, -1 |
| 175 | + ret i32 %ret |
| 176 | +} |
| 177 | + |
| 178 | +define i32 @shl_nsw_nuw_add_nuw(i32 %NBits) { |
| 179 | +; CHECK-LABEL: @shl_nsw_nuw_add_nuw( |
| 180 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl nuw nsw i32 1, [[NBITS:%.*]] |
| 181 | +; CHECK-NEXT: [[RET:%.*]] = add nuw i32 [[SETBIT]], -1 |
| 182 | +; CHECK-NEXT: ret i32 [[RET]] |
| 183 | +; |
| 184 | + %setbit = shl nuw nsw i32 1, %NBits |
| 185 | + %ret = add nuw i32 %setbit, -1 |
| 186 | + ret i32 %ret |
| 187 | +} |
| 188 | + |
| 189 | +define i32 @shl_nsw_nuw_add_nsw_nuw(i32 %NBits) { |
| 190 | +; CHECK-LABEL: @shl_nsw_nuw_add_nsw_nuw( |
| 191 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl nuw nsw i32 1, [[NBITS:%.*]] |
| 192 | +; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[SETBIT]], -1 |
| 193 | +; CHECK-NEXT: ret i32 [[RET]] |
| 194 | +; |
| 195 | + %setbit = shl nuw nsw i32 1, %NBits |
| 196 | + %ret = add nuw nsw i32 %setbit, -1 |
| 197 | + ret i32 %ret |
| 198 | +} |
| 199 | + |
| 200 | +; ============================================================================ ; |
| 201 | +; Vectors |
| 202 | +; ============================================================================ ; |
| 203 | + |
| 204 | +define <2 x i32> @shl_add_vec(<2 x i32> %NBits) { |
| 205 | +; CHECK-LABEL: @shl_add_vec( |
| 206 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl <2 x i32> <i32 1, i32 1>, [[NBITS:%.*]] |
| 207 | +; CHECK-NEXT: [[RET:%.*]] = add <2 x i32> [[SETBIT]], <i32 -1, i32 -1> |
| 208 | +; CHECK-NEXT: ret <2 x i32> [[RET]] |
| 209 | +; |
| 210 | + %setbit = shl <2 x i32> <i32 1, i32 1>, %NBits |
| 211 | + %ret = add <2 x i32> %setbit, <i32 -1, i32 -1> |
| 212 | + ret <2 x i32> %ret |
| 213 | +} |
| 214 | + |
| 215 | +define <3 x i32> @shl_add_vec_undef0(<3 x i32> %NBits) { |
| 216 | +; CHECK-LABEL: @shl_add_vec_undef0( |
| 217 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl <3 x i32> <i32 1, i32 undef, i32 1>, [[NBITS:%.*]] |
| 218 | +; CHECK-NEXT: [[RET:%.*]] = add <3 x i32> [[SETBIT]], <i32 -1, i32 -1, i32 -1> |
| 219 | +; CHECK-NEXT: ret <3 x i32> [[RET]] |
| 220 | +; |
| 221 | + %setbit = shl <3 x i32> <i32 1, i32 undef, i32 1>, %NBits |
| 222 | + %ret = add <3 x i32> %setbit, <i32 -1, i32 -1, i32 -1> |
| 223 | + ret <3 x i32> %ret |
| 224 | +} |
| 225 | + |
| 226 | +define <3 x i32> @shl_add_vec_undef1(<3 x i32> %NBits) { |
| 227 | +; CHECK-LABEL: @shl_add_vec_undef1( |
| 228 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl <3 x i32> <i32 1, i32 1, i32 1>, [[NBITS:%.*]] |
| 229 | +; CHECK-NEXT: [[RET:%.*]] = add <3 x i32> [[SETBIT]], <i32 -1, i32 undef, i32 -1> |
| 230 | +; CHECK-NEXT: ret <3 x i32> [[RET]] |
| 231 | +; |
| 232 | + %setbit = shl <3 x i32> <i32 1, i32 1, i32 1>, %NBits |
| 233 | + %ret = add <3 x i32> %setbit, <i32 -1, i32 undef, i32 -1> |
| 234 | + ret <3 x i32> %ret |
| 235 | +} |
| 236 | + |
| 237 | +define <3 x i32> @shl_add_vec_undef2(<3 x i32> %NBits) { |
| 238 | +; CHECK-LABEL: @shl_add_vec_undef2( |
| 239 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl <3 x i32> <i32 1, i32 undef, i32 1>, [[NBITS:%.*]] |
| 240 | +; CHECK-NEXT: [[RET:%.*]] = add <3 x i32> [[SETBIT]], <i32 -1, i32 undef, i32 -1> |
| 241 | +; CHECK-NEXT: ret <3 x i32> [[RET]] |
| 242 | +; |
| 243 | + %setbit = shl <3 x i32> <i32 1, i32 undef, i32 1>, %NBits |
| 244 | + %ret = add <3 x i32> %setbit, <i32 -1, i32 undef, i32 -1> |
| 245 | + ret <3 x i32> %ret |
| 246 | +} |
| 247 | + |
| 248 | +; ============================================================================ ; |
| 249 | +; Negative tests. Should not be folded. |
| 250 | +; ============================================================================ ; |
| 251 | + |
| 252 | +declare void @use32(i32) |
| 253 | + |
| 254 | +; One use only. |
| 255 | +define i32 @bad_oneuse0(i32 %NBits) { |
| 256 | +; CHECK-LABEL: @bad_oneuse0( |
| 257 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]] |
| 258 | +; CHECK-NEXT: call void @use32(i32 [[SETBIT]]) |
| 259 | +; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], -1 |
| 260 | +; CHECK-NEXT: ret i32 [[RET]] |
| 261 | +; |
| 262 | + %setbit = shl i32 1, %NBits |
| 263 | + call void @use32(i32 %setbit) |
| 264 | + %ret = add i32 %setbit, -1 |
| 265 | + ret i32 %ret |
| 266 | +} |
| 267 | + |
| 268 | +; shift base is not `1` constant |
| 269 | + |
| 270 | +define i32 @bad_shl(i32 %base, i32 %NBits) { |
| 271 | +; CHECK-LABEL: @bad_shl( |
| 272 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 [[BASE:%.*]], [[NBITS:%.*]] |
| 273 | +; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], -1 |
| 274 | +; CHECK-NEXT: ret i32 [[RET]] |
| 275 | +; |
| 276 | + %setbit = shl i32 %base, %NBits ; %base instead of 1 |
| 277 | + %ret = add i32 %setbit, -1 |
| 278 | + ret i32 %ret |
| 279 | +} |
| 280 | + |
| 281 | +; Second `add` operand is not `-1` constant |
| 282 | + |
| 283 | +define i32 @bad_add0(i32 %NBits, i32 %addop2) { |
| 284 | +; CHECK-LABEL: @bad_add0( |
| 285 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]] |
| 286 | +; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], [[ADDOP2:%.*]] |
| 287 | +; CHECK-NEXT: ret i32 [[RET]] |
| 288 | +; |
| 289 | + %setbit = shl i32 1, %NBits |
| 290 | + %ret = add i32 %setbit, %addop2 |
| 291 | + ret i32 %ret |
| 292 | +} |
| 293 | + |
| 294 | +; Bad add constant |
| 295 | + |
| 296 | +define i32 @bad_add1(i32 %NBits) { |
| 297 | +; CHECK-LABEL: @bad_add1( |
| 298 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]] |
| 299 | +; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], 1 |
| 300 | +; CHECK-NEXT: ret i32 [[RET]] |
| 301 | +; |
| 302 | + %setbit = shl i32 1, %NBits |
| 303 | + %ret = add i32 %setbit, 1 ; not -1 |
| 304 | + ret i32 %ret |
| 305 | +} |
| 306 | + |
| 307 | +define i32 @bad_add2(i32 %NBits) { |
| 308 | +; CHECK-LABEL: @bad_add2( |
| 309 | +; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]] |
| 310 | +; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], -2 |
| 311 | +; CHECK-NEXT: ret i32 [[RET]] |
| 312 | +; |
| 313 | + %setbit = shl i32 1, %NBits |
| 314 | + %ret = add i32 %setbit, -2 ; not -1 |
| 315 | + ret i32 %ret |
| 316 | +} |
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