@@ -5,11 +5,11 @@ define i64 @test_shl_nuw_nsw__all_are_safe(i32 %x, i64 %y) {
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5
; CHECK-LABEL: @test_shl_nuw_nsw__all_are_safe(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
8
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
9
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
10
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
11
- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
12
- ; CHECK-NEXT: ret i64 [[TMP6 ]]
8
+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
9
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
10
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
11
+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
12
+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
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;
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%1 = and i32 %x , 15
15
15
%2 = shl nuw nsw i32 %1 , 2
@@ -24,11 +24,11 @@ define i64 @test_shl_nuw__all_are_safe(i32 %x, i64 %y) {
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; CHECK-LABEL: @test_shl_nuw__all_are_safe(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
27
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
28
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
29
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
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- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
31
- ; CHECK-NEXT: ret i64 [[TMP6 ]]
27
+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
28
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
29
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
30
+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
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+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
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;
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%1 = and i32 %x , 15
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%2 = shl nuw i32 %1 , 2
@@ -43,11 +43,11 @@ define i64 @test_shl_nsw__all_are_safe(i32 %x, i64 %y) {
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; CHECK-LABEL: @test_shl_nsw__all_are_safe(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
46
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
47
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
48
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
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- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
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- ; CHECK-NEXT: ret i64 [[TMP6 ]]
46
+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
47
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
48
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
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+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
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+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
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;
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%1 = and i32 %x , 15
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%2 = shl nsw i32 %1 , 2
@@ -62,11 +62,11 @@ define i64 @test_shl__all_are_safe(i32 %x, i64 %y) {
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; CHECK-LABEL: @test_shl__all_are_safe(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
64
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
65
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
66
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
67
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
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- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
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- ; CHECK-NEXT: ret i64 [[TMP6 ]]
65
+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
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+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
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+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
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+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
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+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
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;
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%1 = and i32 %x , 15
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%2 = shl i32 %1 , 2
@@ -81,11 +81,11 @@ define i64 @test_shl_nuw_nsw__nuw_is_safe(i32 %x, i64 %y) {
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; CHECK-LABEL: @test_shl_nuw_nsw__nuw_is_safe(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
84
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
85
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
86
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
87
- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
88
- ; CHECK-NEXT: ret i64 [[TMP6 ]]
84
+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
85
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
86
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
87
+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
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+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
89
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;
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%1 = and i32 %x , 1073741822
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%2 = shl nuw nsw i32 %1 , 2
@@ -100,11 +100,11 @@ define i64 @test_shl_nuw__nuw_is_safe(i32 %x, i64 %y) {
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; CHECK-LABEL: @test_shl_nuw__nuw_is_safe(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
103
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
104
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
105
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
106
- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
107
- ; CHECK-NEXT: ret i64 [[TMP6 ]]
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+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
104
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
105
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
106
+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
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+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
108
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;
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%1 = and i32 %x , 1073741822
110
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%2 = shl nuw i32 %1 , 2
@@ -119,11 +119,11 @@ define i64 @test_shl_nsw__nuw_is_safe(i32 %x, i64 %y) {
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; CHECK-LABEL: @test_shl_nsw__nuw_is_safe(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
122
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
123
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
124
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
125
- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
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- ; CHECK-NEXT: ret i64 [[TMP6 ]]
122
+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
123
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
124
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
125
+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
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+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
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127
;
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%1 = and i32 %x , 1073741822
129
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%2 = shl nsw i32 %1 , 2
@@ -138,11 +138,11 @@ define i64 @test_shl__nuw_is_safe(i32 %x, i64 %y) {
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; CHECK-LABEL: @test_shl__nuw_is_safe(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
141
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
142
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
143
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
144
- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
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- ; CHECK-NEXT: ret i64 [[TMP6 ]]
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+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
142
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
143
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
144
+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
145
+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
146
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;
147
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%1 = and i32 %x , 1073741822
148
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%2 = shl i32 %1 , 2
@@ -234,11 +234,11 @@ define i64 @test_shl_nuw_nsw__none_are_safe(i32 %x, i64 %y) {
234
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; CHECK-LABEL: @test_shl_nuw_nsw__none_are_safe(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
236
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
237
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
238
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
239
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
240
- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
241
- ; CHECK-NEXT: ret i64 [[TMP6 ]]
237
+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
238
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
239
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
240
+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
241
+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
242
242
;
243
243
%1 = and i32 %x , 4294967294
244
244
%2 = shl nuw nsw i32 %1 , 2
@@ -253,11 +253,11 @@ define i64 @test_shl_nuw__none_are_safe(i32 %x, i64 %y) {
253
253
; CHECK-LABEL: @test_shl_nuw__none_are_safe(
254
254
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
255
255
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
256
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
257
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
258
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
259
- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
260
- ; CHECK-NEXT: ret i64 [[TMP6 ]]
256
+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
257
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
258
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
259
+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
260
+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
261
261
;
262
262
%1 = and i32 %x , 4294967294
263
263
%2 = shl nuw i32 %1 , 2
@@ -272,11 +272,11 @@ define i64 @test_shl_nsw__none_are_safe(i32 %x, i64 %y) {
272
272
; CHECK-LABEL: @test_shl_nsw__none_are_safe(
273
273
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
274
274
; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2
275
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
276
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
277
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
278
- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
279
- ; CHECK-NEXT: ret i64 [[TMP6 ]]
275
+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
276
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
277
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
278
+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
279
+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
280
280
;
281
281
%1 = and i32 %x , 4294967294
282
282
%2 = shl nsw i32 %1 , 2
@@ -289,13 +289,11 @@ define i64 @test_shl_nsw__none_are_safe(i32 %x, i64 %y) {
289
289
290
290
define i64 @test_shl__none_are_safe (i32 %x , i64 %y ) {
291
291
; CHECK-LABEL: @test_shl__none_are_safe(
292
- ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], - 2
293
- ; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 2
292
+ ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
293
+ ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
294
294
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
295
- ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
296
- ; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
297
- ; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
298
- ; CHECK-NEXT: ret i64 [[TMP6]]
295
+ ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
296
+ ; CHECK-NEXT: ret i64 [[TMP4]]
299
297
;
300
298
%1 = and i32 %x , 4294967294
301
299
%2 = shl i32 %1 , 2
@@ -310,11 +308,11 @@ define i64 @test_lshr_exact__exact_is_safe(i32 %x, i64 %y) {
310
308
; CHECK-LABEL: @test_lshr_exact__exact_is_safe(
311
309
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
312
310
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
313
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
314
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
315
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
316
- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
317
- ; CHECK-NEXT: ret i64 [[TMP6 ]]
311
+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
312
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
313
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
314
+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
315
+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
318
316
;
319
317
%1 = and i32 %x , 60
320
318
%2 = lshr exact i32 %1 , 2
@@ -329,11 +327,11 @@ define i64 @test_lshr__exact_is_safe(i32 %x, i64 %y) {
329
327
; CHECK-LABEL: @test_lshr__exact_is_safe(
330
328
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
331
329
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
332
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
333
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
334
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
335
- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
336
- ; CHECK-NEXT: ret i64 [[TMP6 ]]
330
+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
331
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
332
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
333
+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
334
+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
337
335
;
338
336
%1 = and i32 %x , 60
339
337
%2 = lshr i32 %1 , 2
@@ -348,11 +346,11 @@ define i64 @test_lshr_exact__exact_is_unsafe(i32 %x, i64 %y) {
348
346
; CHECK-LABEL: @test_lshr_exact__exact_is_unsafe(
349
347
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 63
350
348
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
351
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
352
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
353
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
354
- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
355
- ; CHECK-NEXT: ret i64 [[TMP6 ]]
349
+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
350
+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
351
+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
352
+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
353
+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
356
354
;
357
355
%1 = and i32 %x , 63
358
356
%2 = lshr exact i32 %1 , 2
@@ -365,13 +363,11 @@ define i64 @test_lshr_exact__exact_is_unsafe(i32 %x, i64 %y) {
365
363
366
364
define i64 @test_lshr__exact_is_unsafe (i32 %x , i64 %y ) {
367
365
; CHECK-LABEL: @test_lshr__exact_is_unsafe(
368
- ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 63
369
- ; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
366
+ ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
367
+ ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15
370
368
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
371
- ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
372
- ; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
373
- ; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
374
- ; CHECK-NEXT: ret i64 [[TMP6]]
369
+ ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
370
+ ; CHECK-NEXT: ret i64 [[TMP4]]
375
371
;
376
372
%1 = and i32 %x , 63
377
373
%2 = lshr i32 %1 , 2
@@ -386,11 +382,11 @@ define i64 @test_ashr_exact__exact_is_safe(i32 %x, i64 %y) {
386
382
; CHECK-LABEL: @test_ashr_exact__exact_is_safe(
387
383
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
388
384
; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
389
- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
390
- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
391
- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
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- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
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- ; CHECK-NEXT: ret i64 [[TMP6 ]]
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+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
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+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
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+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
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+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
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+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
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;
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%1 = and i32 %x , -2147483588
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%2 = ashr exact i32 %1 , 2
@@ -405,11 +401,11 @@ define i64 @test_ashr__exact_is_safe(i32 %x, i64 %y) {
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; CHECK-LABEL: @test_ashr__exact_is_safe(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
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; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
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- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
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- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
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- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
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- ; CHECK-NEXT: ret i64 [[TMP6 ]]
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+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
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+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
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+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
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+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
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+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
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;
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%1 = and i32 %x , -2147483588
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%2 = ashr i32 %1 , 2
@@ -424,11 +420,11 @@ define i64 @test_ashr_exact__exact_is_unsafe(i32 %x, i64 %y) {
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; CHECK-LABEL: @test_ashr_exact__exact_is_unsafe(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483585
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; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
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- ; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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- ; CHECK-NEXT: [[TMP4 :%.*]] = icmp eq i32 [[TMP1 ]], 0
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- ; CHECK-NEXT: [[TMP5 :%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
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- ; CHECK-NEXT: [[TMP6 :%.*]] = ashr i64 [[Y:%.*]], [[TMP5 ]]
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- ; CHECK-NEXT: ret i64 [[TMP6 ]]
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+ ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
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+ ; CHECK-NEXT: [[NARROW :%.*]] = select i1 [[TMP3 ]], i32 0, i32 [[TMP2]]
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+ ; CHECK-NEXT: [[TMP4 :%.*]] = zext i32 [[NARROW]] to i64
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+ ; CHECK-NEXT: [[TMP5 :%.*]] = ashr i64 [[Y:%.*]], [[TMP4 ]]
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+ ; CHECK-NEXT: ret i64 [[TMP5 ]]
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;
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%1 = and i32 %x , -2147483585
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%2 = ashr exact i32 %1 , 2
@@ -441,13 +437,11 @@ define i64 @test_ashr_exact__exact_is_unsafe(i32 %x, i64 %y) {
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define i64 @test_ashr__exact_is_unsafe (i32 %x , i64 %y ) {
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; CHECK-LABEL: @test_ashr__exact_is_unsafe(
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- ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483585
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- ; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[TMP1]], 2
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+ ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
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+ ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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- ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
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- ; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
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- ; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
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- ; CHECK-NEXT: ret i64 [[TMP6]]
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+ ; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
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+ ; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%1 = and i32 %x , -2147483585
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%2 = ashr i32 %1 , 2
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