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committedMay 31, 2018
[InstCombine] narrow select to match condition operands' size
This is the planned enhancement to D47163 / rL333611. We want to match cmp/select sizes because that will be recognized as min/max more easily and lead to better codegen (especially for vector types). As mentioned in D47163, this improves some of the tests that would also be folded by D46380, so we may want to adjust that patch to match the new patterns where the extend op occurs after the select. llvm-svn: 333689
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4 files changed

+133
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‎llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1164,6 +1164,11 @@ static Instruction *foldAddSubSelect(SelectInst &SI,
11641164
}
11651165

11661166
Instruction *InstCombiner::foldSelectExtConst(SelectInst &Sel) {
1167+
Constant *C;
1168+
if (!match(Sel.getTrueValue(), m_Constant(C)) &&
1169+
!match(Sel.getFalseValue(), m_Constant(C)))
1170+
return nullptr;
1171+
11671172
Instruction *ExtInst;
11681173
if (!match(Sel.getTrueValue(), m_Instruction(ExtInst)) &&
11691174
!match(Sel.getFalseValue(), m_Instruction(ExtInst)))
@@ -1173,20 +1178,18 @@ Instruction *InstCombiner::foldSelectExtConst(SelectInst &Sel) {
11731178
if (ExtOpcode != Instruction::ZExt && ExtOpcode != Instruction::SExt)
11741179
return nullptr;
11751180

1176-
// TODO: Handle larger types? That requires adjusting FoldOpIntoSelect too.
1181+
// If we are extending from a boolean type or if we can create a select that
1182+
// has the same size operands as its condition, try to narrow the select.
11771183
Value *X = ExtInst->getOperand(0);
11781184
Type *SmallType = X->getType();
1179-
if (!SmallType->isIntOrIntVectorTy(1))
1180-
return nullptr;
1181-
1182-
Constant *C;
1183-
if (!match(Sel.getTrueValue(), m_Constant(C)) &&
1184-
!match(Sel.getFalseValue(), m_Constant(C)))
1185+
Value *Cond = Sel.getCondition();
1186+
auto *Cmp = dyn_cast<CmpInst>(Cond);
1187+
if (!SmallType->isIntOrIntVectorTy(1) &&
1188+
(!Cmp || Cmp->getOperand(0)->getType() != SmallType))
11851189
return nullptr;
11861190

11871191
// If the constant is the same after truncation to the smaller type and
11881192
// extension to the original type, we can narrow the select.
1189-
Value *Cond = Sel.getCondition();
11901193
Type *SelType = Sel.getType();
11911194
Constant *TruncC = ConstantExpr::getTrunc(C, SmallType);
11921195
Constant *ExtC = ConstantExpr::getCast(ExtOpcode, TruncC, SelType);

‎llvm/test/Transforms/InstCombine/minmax-fold.ll

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -19,9 +19,9 @@ define i64 @t1(i32 %a) {
1919
define i64 @t2(i32 %a) {
2020
; CHECK-LABEL: @t2(
2121
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 5
22-
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
23-
; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[TMP2]] to i64
24-
; CHECK-NEXT: ret i64 [[TMP3]]
22+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
23+
; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[NARROW]] to i64
24+
; CHECK-NEXT: ret i64 [[TMP2]]
2525
;
2626
%1 = icmp slt i32 %a, 5
2727
%2 = sext i32 %a to i64
@@ -33,9 +33,9 @@ define i64 @t2(i32 %a) {
3333
define i64 @t3(i32 %a) {
3434
; CHECK-LABEL: @t3(
3535
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[A:%.*]], 5
36-
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
37-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
38-
; CHECK-NEXT: ret i64 [[TMP3]]
36+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
37+
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[NARROW]] to i64
38+
; CHECK-NEXT: ret i64 [[TMP2]]
3939
;
4040
%1 = icmp ult i32 %a, 5
4141
%2 = zext i32 %a to i64
@@ -58,13 +58,12 @@ define i32 @t4(i64 %a) {
5858
}
5959

6060
; Same as @t3, but with mismatched signedness between icmp and zext.
61-
; InstCombine should leave this alone.
6261
define i64 @t5(i32 %a) {
6362
; CHECK-LABEL: @t5(
64-
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 5
65-
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[A]] to i64
66-
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i64 5, i64 [[TMP2]]
67-
; CHECK-NEXT: ret i64 [[TMP3]]
63+
; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[A:%.*]], 5
64+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
65+
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[NARROW]] to i64
66+
; CHECK-NEXT: ret i64 [[TMP2]]
6867
;
6968
%1 = icmp slt i32 %a, 5
7069
%2 = zext i32 %a to i64

‎llvm/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@ define i64 @sel_false_val_is_a_masked_shl_of_true_val1(i32 %x, i64 %y) {
55
; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val1(
66
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
77
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
8-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
9-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
10-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
11-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
12-
; CHECK-NEXT: ret i64 [[TMP6]]
8+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
9+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
10+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
11+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
12+
; CHECK-NEXT: ret i64 [[TMP5]]
1313
;
1414
%1 = and i32 %x, 15
1515
%2 = shl nuw nsw i32 %1, 2
@@ -41,11 +41,11 @@ define i64 @sel_false_val_is_a_masked_lshr_of_true_val1(i32 %x, i64 %y) {
4141
; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val1(
4242
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
4343
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
44-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
45-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
46-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
47-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
48-
; CHECK-NEXT: ret i64 [[TMP6]]
44+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
45+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
46+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
47+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
48+
; CHECK-NEXT: ret i64 [[TMP5]]
4949
;
5050
%1 = and i32 %x, 60
5151
%2 = lshr i32 %1, 2
@@ -77,11 +77,11 @@ define i64 @sel_false_val_is_a_masked_ashr_of_true_val1(i32 %x, i64 %y) {
7777
; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val1(
7878
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
7979
; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
80-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
81-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
82-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
83-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
84-
; CHECK-NEXT: ret i64 [[TMP6]]
80+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
81+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
82+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
83+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
84+
; CHECK-NEXT: ret i64 [[TMP5]]
8585
;
8686
%1 = and i32 %x, -2147483588
8787
%2 = ashr i32 %1, 2

‎llvm/test/Transforms/InstCombine/select-obo-peo-ops.ll

Lines changed: 97 additions & 103 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@ define i64 @test_shl_nuw_nsw__all_are_safe(i32 %x, i64 %y) {
55
; CHECK-LABEL: @test_shl_nuw_nsw__all_are_safe(
66
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
77
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
8-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
9-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
10-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
11-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
12-
; CHECK-NEXT: ret i64 [[TMP6]]
8+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
9+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
10+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
11+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
12+
; CHECK-NEXT: ret i64 [[TMP5]]
1313
;
1414
%1 = and i32 %x, 15
1515
%2 = shl nuw nsw i32 %1, 2
@@ -24,11 +24,11 @@ define i64 @test_shl_nuw__all_are_safe(i32 %x, i64 %y) {
2424
; CHECK-LABEL: @test_shl_nuw__all_are_safe(
2525
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
2626
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
27-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
28-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
29-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
30-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
31-
; CHECK-NEXT: ret i64 [[TMP6]]
27+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
28+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
29+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
30+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
31+
; CHECK-NEXT: ret i64 [[TMP5]]
3232
;
3333
%1 = and i32 %x, 15
3434
%2 = shl nuw i32 %1, 2
@@ -43,11 +43,11 @@ define i64 @test_shl_nsw__all_are_safe(i32 %x, i64 %y) {
4343
; CHECK-LABEL: @test_shl_nsw__all_are_safe(
4444
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
4545
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
46-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
47-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
48-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
49-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
50-
; CHECK-NEXT: ret i64 [[TMP6]]
46+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
47+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
48+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
49+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
50+
; CHECK-NEXT: ret i64 [[TMP5]]
5151
;
5252
%1 = and i32 %x, 15
5353
%2 = shl nsw i32 %1, 2
@@ -62,11 +62,11 @@ define i64 @test_shl__all_are_safe(i32 %x, i64 %y) {
6262
; CHECK-LABEL: @test_shl__all_are_safe(
6363
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
6464
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
65-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
66-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
67-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
68-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
69-
; CHECK-NEXT: ret i64 [[TMP6]]
65+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
66+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
67+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
68+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
69+
; CHECK-NEXT: ret i64 [[TMP5]]
7070
;
7171
%1 = and i32 %x, 15
7272
%2 = shl i32 %1, 2
@@ -81,11 +81,11 @@ define i64 @test_shl_nuw_nsw__nuw_is_safe(i32 %x, i64 %y) {
8181
; CHECK-LABEL: @test_shl_nuw_nsw__nuw_is_safe(
8282
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
8383
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
84-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
85-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
86-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
87-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
88-
; CHECK-NEXT: ret i64 [[TMP6]]
84+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
85+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
86+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
87+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
88+
; CHECK-NEXT: ret i64 [[TMP5]]
8989
;
9090
%1 = and i32 %x, 1073741822
9191
%2 = shl nuw nsw i32 %1, 2
@@ -100,11 +100,11 @@ define i64 @test_shl_nuw__nuw_is_safe(i32 %x, i64 %y) {
100100
; CHECK-LABEL: @test_shl_nuw__nuw_is_safe(
101101
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
102102
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
103-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
104-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
105-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
106-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
107-
; CHECK-NEXT: ret i64 [[TMP6]]
103+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
104+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
105+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
106+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
107+
; CHECK-NEXT: ret i64 [[TMP5]]
108108
;
109109
%1 = and i32 %x, 1073741822
110110
%2 = shl nuw i32 %1, 2
@@ -119,11 +119,11 @@ define i64 @test_shl_nsw__nuw_is_safe(i32 %x, i64 %y) {
119119
; CHECK-LABEL: @test_shl_nsw__nuw_is_safe(
120120
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
121121
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
122-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
123-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
124-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
125-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
126-
; CHECK-NEXT: ret i64 [[TMP6]]
122+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
123+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
124+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
125+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
126+
; CHECK-NEXT: ret i64 [[TMP5]]
127127
;
128128
%1 = and i32 %x, 1073741822
129129
%2 = shl nsw i32 %1, 2
@@ -138,11 +138,11 @@ define i64 @test_shl__nuw_is_safe(i32 %x, i64 %y) {
138138
; CHECK-LABEL: @test_shl__nuw_is_safe(
139139
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741822
140140
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
141-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
142-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
143-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
144-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
145-
; CHECK-NEXT: ret i64 [[TMP6]]
141+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
142+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
143+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
144+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
145+
; CHECK-NEXT: ret i64 [[TMP5]]
146146
;
147147
%1 = and i32 %x, 1073741822
148148
%2 = shl i32 %1, 2
@@ -234,11 +234,11 @@ define i64 @test_shl_nuw_nsw__none_are_safe(i32 %x, i64 %y) {
234234
; CHECK-LABEL: @test_shl_nuw_nsw__none_are_safe(
235235
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
236236
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
237-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
238-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
239-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
240-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
241-
; CHECK-NEXT: ret i64 [[TMP6]]
237+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
238+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
239+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
240+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
241+
; CHECK-NEXT: ret i64 [[TMP5]]
242242
;
243243
%1 = and i32 %x, 4294967294
244244
%2 = shl nuw nsw i32 %1, 2
@@ -253,11 +253,11 @@ define i64 @test_shl_nuw__none_are_safe(i32 %x, i64 %y) {
253253
; CHECK-LABEL: @test_shl_nuw__none_are_safe(
254254
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
255255
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i32 [[TMP1]], 2
256-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
257-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
258-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
259-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
260-
; CHECK-NEXT: ret i64 [[TMP6]]
256+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
257+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
258+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
259+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
260+
; CHECK-NEXT: ret i64 [[TMP5]]
261261
;
262262
%1 = and i32 %x, 4294967294
263263
%2 = shl nuw i32 %1, 2
@@ -272,11 +272,11 @@ define i64 @test_shl_nsw__none_are_safe(i32 %x, i64 %y) {
272272
; CHECK-LABEL: @test_shl_nsw__none_are_safe(
273273
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
274274
; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2
275-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
276-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
277-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
278-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
279-
; CHECK-NEXT: ret i64 [[TMP6]]
275+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
276+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
277+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
278+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
279+
; CHECK-NEXT: ret i64 [[TMP5]]
280280
;
281281
%1 = and i32 %x, 4294967294
282282
%2 = shl nsw i32 %1, 2
@@ -289,13 +289,11 @@ define i64 @test_shl_nsw__none_are_safe(i32 %x, i64 %y) {
289289

290290
define i64 @test_shl__none_are_safe(i32 %x, i64 %y) {
291291
; CHECK-LABEL: @test_shl__none_are_safe(
292-
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2
293-
; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], 2
292+
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
293+
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8
294294
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
295-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
296-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
297-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
298-
; CHECK-NEXT: ret i64 [[TMP6]]
295+
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
296+
; CHECK-NEXT: ret i64 [[TMP4]]
299297
;
300298
%1 = and i32 %x, 4294967294
301299
%2 = shl i32 %1, 2
@@ -310,11 +308,11 @@ define i64 @test_lshr_exact__exact_is_safe(i32 %x, i64 %y) {
310308
; CHECK-LABEL: @test_lshr_exact__exact_is_safe(
311309
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
312310
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
313-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
314-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
315-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
316-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
317-
; CHECK-NEXT: ret i64 [[TMP6]]
311+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
312+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
313+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
314+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
315+
; CHECK-NEXT: ret i64 [[TMP5]]
318316
;
319317
%1 = and i32 %x, 60
320318
%2 = lshr exact i32 %1, 2
@@ -329,11 +327,11 @@ define i64 @test_lshr__exact_is_safe(i32 %x, i64 %y) {
329327
; CHECK-LABEL: @test_lshr__exact_is_safe(
330328
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
331329
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
332-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
333-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
334-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
335-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
336-
; CHECK-NEXT: ret i64 [[TMP6]]
330+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
331+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
332+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
333+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
334+
; CHECK-NEXT: ret i64 [[TMP5]]
337335
;
338336
%1 = and i32 %x, 60
339337
%2 = lshr i32 %1, 2
@@ -348,11 +346,11 @@ define i64 @test_lshr_exact__exact_is_unsafe(i32 %x, i64 %y) {
348346
; CHECK-LABEL: @test_lshr_exact__exact_is_unsafe(
349347
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 63
350348
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
351-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
352-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
353-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
354-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
355-
; CHECK-NEXT: ret i64 [[TMP6]]
349+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
350+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
351+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
352+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
353+
; CHECK-NEXT: ret i64 [[TMP5]]
356354
;
357355
%1 = and i32 %x, 63
358356
%2 = lshr exact i32 %1, 2
@@ -365,13 +363,11 @@ define i64 @test_lshr_exact__exact_is_unsafe(i32 %x, i64 %y) {
365363

366364
define i64 @test_lshr__exact_is_unsafe(i32 %x, i64 %y) {
367365
; CHECK-LABEL: @test_lshr__exact_is_unsafe(
368-
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 63
369-
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
366+
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
367+
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15
370368
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
371-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
372-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
373-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
374-
; CHECK-NEXT: ret i64 [[TMP6]]
369+
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
370+
; CHECK-NEXT: ret i64 [[TMP4]]
375371
;
376372
%1 = and i32 %x, 63
377373
%2 = lshr i32 %1, 2
@@ -386,11 +382,11 @@ define i64 @test_ashr_exact__exact_is_safe(i32 %x, i64 %y) {
386382
; CHECK-LABEL: @test_ashr_exact__exact_is_safe(
387383
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
388384
; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
389-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
390-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
391-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
392-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
393-
; CHECK-NEXT: ret i64 [[TMP6]]
385+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
386+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
387+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
388+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
389+
; CHECK-NEXT: ret i64 [[TMP5]]
394390
;
395391
%1 = and i32 %x, -2147483588
396392
%2 = ashr exact i32 %1, 2
@@ -405,11 +401,11 @@ define i64 @test_ashr__exact_is_safe(i32 %x, i64 %y) {
405401
; CHECK-LABEL: @test_ashr__exact_is_safe(
406402
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
407403
; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
408-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
409-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
410-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
411-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
412-
; CHECK-NEXT: ret i64 [[TMP6]]
404+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
405+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
406+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
407+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
408+
; CHECK-NEXT: ret i64 [[TMP5]]
413409
;
414410
%1 = and i32 %x, -2147483588
415411
%2 = ashr i32 %1, 2
@@ -424,11 +420,11 @@ define i64 @test_ashr_exact__exact_is_unsafe(i32 %x, i64 %y) {
424420
; CHECK-LABEL: @test_ashr_exact__exact_is_unsafe(
425421
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483585
426422
; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
427-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
428-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
429-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
430-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
431-
; CHECK-NEXT: ret i64 [[TMP6]]
423+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
424+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
425+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
426+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
427+
; CHECK-NEXT: ret i64 [[TMP5]]
432428
;
433429
%1 = and i32 %x, -2147483585
434430
%2 = ashr exact i32 %1, 2
@@ -441,13 +437,11 @@ define i64 @test_ashr_exact__exact_is_unsafe(i32 %x, i64 %y) {
441437

442438
define i64 @test_ashr__exact_is_unsafe(i32 %x, i64 %y) {
443439
; CHECK-LABEL: @test_ashr__exact_is_unsafe(
444-
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483585
445-
; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[TMP1]], 2
440+
; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
441+
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
446442
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
447-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
448-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
449-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
450-
; CHECK-NEXT: ret i64 [[TMP6]]
443+
; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
444+
; CHECK-NEXT: ret i64 [[TMP4]]
451445
;
452446
%1 = and i32 %x, -2147483585
453447
%2 = ashr i32 %1, 2

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