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rotaterightrotateright
committedMay 31, 2018
[InstCombine] narrow select to match condition operands' size
This is the planned enhancement to D47163 / rL333611. We want to match cmp/select sizes because that will be recognized as min/max more easily and lead to better codegen (especially for vector types). As mentioned in D47163, this improves some of the tests that would also be folded by D46380, so we may want to adjust that patch to match the new patterns where the extend op occurs after the select. llvm-svn: 333689
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4 files changed

+133
-137
lines changed

4 files changed

+133
-137
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‎llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

+11-8
Original file line numberDiff line numberDiff line change
@@ -1164,6 +1164,11 @@ static Instruction *foldAddSubSelect(SelectInst &SI,
11641164
}
11651165

11661166
Instruction *InstCombiner::foldSelectExtConst(SelectInst &Sel) {
1167+
Constant *C;
1168+
if (!match(Sel.getTrueValue(), m_Constant(C)) &&
1169+
!match(Sel.getFalseValue(), m_Constant(C)))
1170+
return nullptr;
1171+
11671172
Instruction *ExtInst;
11681173
if (!match(Sel.getTrueValue(), m_Instruction(ExtInst)) &&
11691174
!match(Sel.getFalseValue(), m_Instruction(ExtInst)))
@@ -1173,20 +1178,18 @@ Instruction *InstCombiner::foldSelectExtConst(SelectInst &Sel) {
11731178
if (ExtOpcode != Instruction::ZExt && ExtOpcode != Instruction::SExt)
11741179
return nullptr;
11751180

1176-
// TODO: Handle larger types? That requires adjusting FoldOpIntoSelect too.
1181+
// If we are extending from a boolean type or if we can create a select that
1182+
// has the same size operands as its condition, try to narrow the select.
11771183
Value *X = ExtInst->getOperand(0);
11781184
Type *SmallType = X->getType();
1179-
if (!SmallType->isIntOrIntVectorTy(1))
1180-
return nullptr;
1181-
1182-
Constant *C;
1183-
if (!match(Sel.getTrueValue(), m_Constant(C)) &&
1184-
!match(Sel.getFalseValue(), m_Constant(C)))
1185+
Value *Cond = Sel.getCondition();
1186+
auto *Cmp = dyn_cast<CmpInst>(Cond);
1187+
if (!SmallType->isIntOrIntVectorTy(1) &&
1188+
(!Cmp || Cmp->getOperand(0)->getType() != SmallType))
11851189
return nullptr;
11861190

11871191
// If the constant is the same after truncation to the smaller type and
11881192
// extension to the original type, we can narrow the select.
1189-
Value *Cond = Sel.getCondition();
11901193
Type *SelType = Sel.getType();
11911194
Constant *TruncC = ConstantExpr::getTrunc(C, SmallType);
11921195
Constant *ExtC = ConstantExpr::getCast(ExtOpcode, TruncC, SelType);

‎llvm/test/Transforms/InstCombine/minmax-fold.ll

+10-11
Original file line numberDiff line numberDiff line change
@@ -19,9 +19,9 @@ define i64 @t1(i32 %a) {
1919
define i64 @t2(i32 %a) {
2020
; CHECK-LABEL: @t2(
2121
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 5
22-
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
23-
; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[TMP2]] to i64
24-
; CHECK-NEXT: ret i64 [[TMP3]]
22+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
23+
; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[NARROW]] to i64
24+
; CHECK-NEXT: ret i64 [[TMP2]]
2525
;
2626
%1 = icmp slt i32 %a, 5
2727
%2 = sext i32 %a to i64
@@ -33,9 +33,9 @@ define i64 @t2(i32 %a) {
3333
define i64 @t3(i32 %a) {
3434
; CHECK-LABEL: @t3(
3535
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[A:%.*]], 5
36-
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
37-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
38-
; CHECK-NEXT: ret i64 [[TMP3]]
36+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
37+
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[NARROW]] to i64
38+
; CHECK-NEXT: ret i64 [[TMP2]]
3939
;
4040
%1 = icmp ult i32 %a, 5
4141
%2 = zext i32 %a to i64
@@ -58,13 +58,12 @@ define i32 @t4(i64 %a) {
5858
}
5959

6060
; Same as @t3, but with mismatched signedness between icmp and zext.
61-
; InstCombine should leave this alone.
6261
define i64 @t5(i32 %a) {
6362
; CHECK-LABEL: @t5(
64-
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 5
65-
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[A]] to i64
66-
; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i64 5, i64 [[TMP2]]
67-
; CHECK-NEXT: ret i64 [[TMP3]]
63+
; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[A:%.*]], 5
64+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP1]], i32 [[A]], i32 5
65+
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[NARROW]] to i64
66+
; CHECK-NEXT: ret i64 [[TMP2]]
6867
;
6968
%1 = icmp slt i32 %a, 5
7069
%2 = zext i32 %a to i64

‎llvm/test/Transforms/InstCombine/select-bitext-bitwise-ops.ll

+15-15
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@ define i64 @sel_false_val_is_a_masked_shl_of_true_val1(i32 %x, i64 %y) {
55
; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val1(
66
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
77
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
8-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
9-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
10-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
11-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
12-
; CHECK-NEXT: ret i64 [[TMP6]]
8+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
9+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
10+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
11+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
12+
; CHECK-NEXT: ret i64 [[TMP5]]
1313
;
1414
%1 = and i32 %x, 15
1515
%2 = shl nuw nsw i32 %1, 2
@@ -41,11 +41,11 @@ define i64 @sel_false_val_is_a_masked_lshr_of_true_val1(i32 %x, i64 %y) {
4141
; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val1(
4242
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
4343
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
44-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
45-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
46-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
47-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
48-
; CHECK-NEXT: ret i64 [[TMP6]]
44+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
45+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
46+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
47+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
48+
; CHECK-NEXT: ret i64 [[TMP5]]
4949
;
5050
%1 = and i32 %x, 60
5151
%2 = lshr i32 %1, 2
@@ -77,11 +77,11 @@ define i64 @sel_false_val_is_a_masked_ashr_of_true_val1(i32 %x, i64 %y) {
7777
; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val1(
7878
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
7979
; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
80-
; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
81-
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP1]], 0
82-
; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i64 0, i64 [[TMP3]]
83-
; CHECK-NEXT: [[TMP6:%.*]] = ashr i64 [[Y:%.*]], [[TMP5]]
84-
; CHECK-NEXT: ret i64 [[TMP6]]
80+
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
81+
; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
82+
; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
83+
; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
84+
; CHECK-NEXT: ret i64 [[TMP5]]
8585
;
8686
%1 = and i32 %x, -2147483588
8787
%2 = ashr i32 %1, 2

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