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JDevlieghereJDevlieghere
committedMay 29, 2018
[CodeView] Add prefix to CodeView registers.
Adds CVReg to CodeView register names to prevent a duplicate symbol with CR3 defined in termios.h, as suggested by Zachary on the mailing list. http://lists.llvm.org/pipermail/llvm-dev/2018-May/123372.html Differential revision: https://reviews.llvm.org/D47478 rdar://39863705 llvm-svn: 333421
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12 files changed

+370
-370
lines changed

12 files changed

+370
-370
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‎llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def

+224-224
Large diffs are not rendered by default.

‎llvm/lib/DebugInfo/PDB/Native/NativeRawSymbol.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -188,7 +188,7 @@ uint32_t NativeRawSymbol::getLiveRangeStartRelativeVirtualAddress() const {
188188
}
189189

190190
codeview::RegisterId NativeRawSymbol::getLocalBasePointerRegisterId() const {
191-
return codeview::RegisterId::EAX;
191+
return codeview::RegisterId::CVRegEAX;
192192
}
193193

194194
uint32_t NativeRawSymbol::getLowerBoundId() const {
@@ -248,7 +248,7 @@ uint32_t NativeRawSymbol::getRank() const {
248248
}
249249

250250
codeview::RegisterId NativeRawSymbol::getRegisterId() const {
251-
return codeview::RegisterId::EAX;
251+
return codeview::RegisterId::CVRegEAX;
252252
}
253253

254254
uint32_t NativeRawSymbol::getRegisterType() const {

‎llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

+114-114
Original file line numberDiff line numberDiff line change
@@ -78,120 +78,120 @@ void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
7878
codeview::RegisterId CVReg;
7979
MCPhysReg Reg;
8080
} RegMap[] = {
81-
{ codeview::RegisterId::AL, X86::AL},
82-
{ codeview::RegisterId::CL, X86::CL},
83-
{ codeview::RegisterId::DL, X86::DL},
84-
{ codeview::RegisterId::BL, X86::BL},
85-
{ codeview::RegisterId::AH, X86::AH},
86-
{ codeview::RegisterId::CH, X86::CH},
87-
{ codeview::RegisterId::DH, X86::DH},
88-
{ codeview::RegisterId::BH, X86::BH},
89-
{ codeview::RegisterId::AX, X86::AX},
90-
{ codeview::RegisterId::CX, X86::CX},
91-
{ codeview::RegisterId::DX, X86::DX},
92-
{ codeview::RegisterId::BX, X86::BX},
93-
{ codeview::RegisterId::SP, X86::SP},
94-
{ codeview::RegisterId::BP, X86::BP},
95-
{ codeview::RegisterId::SI, X86::SI},
96-
{ codeview::RegisterId::DI, X86::DI},
97-
{ codeview::RegisterId::EAX, X86::EAX},
98-
{ codeview::RegisterId::ECX, X86::ECX},
99-
{ codeview::RegisterId::EDX, X86::EDX},
100-
{ codeview::RegisterId::EBX, X86::EBX},
101-
{ codeview::RegisterId::ESP, X86::ESP},
102-
{ codeview::RegisterId::EBP, X86::EBP},
103-
{ codeview::RegisterId::ESI, X86::ESI},
104-
{ codeview::RegisterId::EDI, X86::EDI},
105-
106-
{ codeview::RegisterId::EFLAGS, X86::EFLAGS},
107-
108-
{ codeview::RegisterId::ST0, X86::FP0},
109-
{ codeview::RegisterId::ST1, X86::FP1},
110-
{ codeview::RegisterId::ST2, X86::FP2},
111-
{ codeview::RegisterId::ST3, X86::FP3},
112-
{ codeview::RegisterId::ST4, X86::FP4},
113-
{ codeview::RegisterId::ST5, X86::FP5},
114-
{ codeview::RegisterId::ST6, X86::FP6},
115-
{ codeview::RegisterId::ST7, X86::FP7},
116-
117-
{ codeview::RegisterId::XMM0, X86::XMM0},
118-
{ codeview::RegisterId::XMM1, X86::XMM1},
119-
{ codeview::RegisterId::XMM2, X86::XMM2},
120-
{ codeview::RegisterId::XMM3, X86::XMM3},
121-
{ codeview::RegisterId::XMM4, X86::XMM4},
122-
{ codeview::RegisterId::XMM5, X86::XMM5},
123-
{ codeview::RegisterId::XMM6, X86::XMM6},
124-
{ codeview::RegisterId::XMM7, X86::XMM7},
125-
126-
{ codeview::RegisterId::XMM8, X86::XMM8},
127-
{ codeview::RegisterId::XMM9, X86::XMM9},
128-
{ codeview::RegisterId::XMM10, X86::XMM10},
129-
{ codeview::RegisterId::XMM11, X86::XMM11},
130-
{ codeview::RegisterId::XMM12, X86::XMM12},
131-
{ codeview::RegisterId::XMM13, X86::XMM13},
132-
{ codeview::RegisterId::XMM14, X86::XMM14},
133-
{ codeview::RegisterId::XMM15, X86::XMM15},
134-
135-
{ codeview::RegisterId::SIL, X86::SIL},
136-
{ codeview::RegisterId::DIL, X86::DIL},
137-
{ codeview::RegisterId::BPL, X86::BPL},
138-
{ codeview::RegisterId::SPL, X86::SPL},
139-
{ codeview::RegisterId::RAX, X86::RAX},
140-
{ codeview::RegisterId::RBX, X86::RBX},
141-
{ codeview::RegisterId::RCX, X86::RCX},
142-
{ codeview::RegisterId::RDX, X86::RDX},
143-
{ codeview::RegisterId::RSI, X86::RSI},
144-
{ codeview::RegisterId::RDI, X86::RDI},
145-
{ codeview::RegisterId::RBP, X86::RBP},
146-
{ codeview::RegisterId::RSP, X86::RSP},
147-
{ codeview::RegisterId::R8, X86::R8},
148-
{ codeview::RegisterId::R9, X86::R9},
149-
{ codeview::RegisterId::R10, X86::R10},
150-
{ codeview::RegisterId::R11, X86::R11},
151-
{ codeview::RegisterId::R12, X86::R12},
152-
{ codeview::RegisterId::R13, X86::R13},
153-
{ codeview::RegisterId::R14, X86::R14},
154-
{ codeview::RegisterId::R15, X86::R15},
155-
{ codeview::RegisterId::R8B, X86::R8B},
156-
{ codeview::RegisterId::R9B, X86::R9B},
157-
{ codeview::RegisterId::R10B, X86::R10B},
158-
{ codeview::RegisterId::R11B, X86::R11B},
159-
{ codeview::RegisterId::R12B, X86::R12B},
160-
{ codeview::RegisterId::R13B, X86::R13B},
161-
{ codeview::RegisterId::R14B, X86::R14B},
162-
{ codeview::RegisterId::R15B, X86::R15B},
163-
{ codeview::RegisterId::R8W, X86::R8W},
164-
{ codeview::RegisterId::R9W, X86::R9W},
165-
{ codeview::RegisterId::R10W, X86::R10W},
166-
{ codeview::RegisterId::R11W, X86::R11W},
167-
{ codeview::RegisterId::R12W, X86::R12W},
168-
{ codeview::RegisterId::R13W, X86::R13W},
169-
{ codeview::RegisterId::R14W, X86::R14W},
170-
{ codeview::RegisterId::R15W, X86::R15W},
171-
{ codeview::RegisterId::R8D, X86::R8D},
172-
{ codeview::RegisterId::R9D, X86::R9D},
173-
{ codeview::RegisterId::R10D, X86::R10D},
174-
{ codeview::RegisterId::R11D, X86::R11D},
175-
{ codeview::RegisterId::R12D, X86::R12D},
176-
{ codeview::RegisterId::R13D, X86::R13D},
177-
{ codeview::RegisterId::R14D, X86::R14D},
178-
{ codeview::RegisterId::R15D, X86::R15D},
179-
{ codeview::RegisterId::AMD64_YMM0, X86::YMM0},
180-
{ codeview::RegisterId::AMD64_YMM1, X86::YMM1},
181-
{ codeview::RegisterId::AMD64_YMM2, X86::YMM2},
182-
{ codeview::RegisterId::AMD64_YMM3, X86::YMM3},
183-
{ codeview::RegisterId::AMD64_YMM4, X86::YMM4},
184-
{ codeview::RegisterId::AMD64_YMM5, X86::YMM5},
185-
{ codeview::RegisterId::AMD64_YMM6, X86::YMM6},
186-
{ codeview::RegisterId::AMD64_YMM7, X86::YMM7},
187-
{ codeview::RegisterId::AMD64_YMM8, X86::YMM8},
188-
{ codeview::RegisterId::AMD64_YMM9, X86::YMM9},
189-
{ codeview::RegisterId::AMD64_YMM10, X86::YMM10},
190-
{ codeview::RegisterId::AMD64_YMM11, X86::YMM11},
191-
{ codeview::RegisterId::AMD64_YMM12, X86::YMM12},
192-
{ codeview::RegisterId::AMD64_YMM13, X86::YMM13},
193-
{ codeview::RegisterId::AMD64_YMM14, X86::YMM14},
194-
{ codeview::RegisterId::AMD64_YMM15, X86::YMM15},
81+
{ codeview::RegisterId::CVRegAL, X86::AL},
82+
{ codeview::RegisterId::CVRegCL, X86::CL},
83+
{ codeview::RegisterId::CVRegDL, X86::DL},
84+
{ codeview::RegisterId::CVRegBL, X86::BL},
85+
{ codeview::RegisterId::CVRegAH, X86::AH},
86+
{ codeview::RegisterId::CVRegCH, X86::CH},
87+
{ codeview::RegisterId::CVRegDH, X86::DH},
88+
{ codeview::RegisterId::CVRegBH, X86::BH},
89+
{ codeview::RegisterId::CVRegAX, X86::AX},
90+
{ codeview::RegisterId::CVRegCX, X86::CX},
91+
{ codeview::RegisterId::CVRegDX, X86::DX},
92+
{ codeview::RegisterId::CVRegBX, X86::BX},
93+
{ codeview::RegisterId::CVRegSP, X86::SP},
94+
{ codeview::RegisterId::CVRegBP, X86::BP},
95+
{ codeview::RegisterId::CVRegSI, X86::SI},
96+
{ codeview::RegisterId::CVRegDI, X86::DI},
97+
{ codeview::RegisterId::CVRegEAX, X86::EAX},
98+
{ codeview::RegisterId::CVRegECX, X86::ECX},
99+
{ codeview::RegisterId::CVRegEDX, X86::EDX},
100+
{ codeview::RegisterId::CVRegEBX, X86::EBX},
101+
{ codeview::RegisterId::CVRegESP, X86::ESP},
102+
{ codeview::RegisterId::CVRegEBP, X86::EBP},
103+
{ codeview::RegisterId::CVRegESI, X86::ESI},
104+
{ codeview::RegisterId::CVRegEDI, X86::EDI},
105+
106+
{ codeview::RegisterId::CVRegEFLAGS, X86::EFLAGS},
107+
108+
{ codeview::RegisterId::CVRegST0, X86::FP0},
109+
{ codeview::RegisterId::CVRegST1, X86::FP1},
110+
{ codeview::RegisterId::CVRegST2, X86::FP2},
111+
{ codeview::RegisterId::CVRegST3, X86::FP3},
112+
{ codeview::RegisterId::CVRegST4, X86::FP4},
113+
{ codeview::RegisterId::CVRegST5, X86::FP5},
114+
{ codeview::RegisterId::CVRegST6, X86::FP6},
115+
{ codeview::RegisterId::CVRegST7, X86::FP7},
116+
117+
{ codeview::RegisterId::CVRegXMM0, X86::XMM0},
118+
{ codeview::RegisterId::CVRegXMM1, X86::XMM1},
119+
{ codeview::RegisterId::CVRegXMM2, X86::XMM2},
120+
{ codeview::RegisterId::CVRegXMM3, X86::XMM3},
121+
{ codeview::RegisterId::CVRegXMM4, X86::XMM4},
122+
{ codeview::RegisterId::CVRegXMM5, X86::XMM5},
123+
{ codeview::RegisterId::CVRegXMM6, X86::XMM6},
124+
{ codeview::RegisterId::CVRegXMM7, X86::XMM7},
125+
126+
{ codeview::RegisterId::CVRegXMM8, X86::XMM8},
127+
{ codeview::RegisterId::CVRegXMM9, X86::XMM9},
128+
{ codeview::RegisterId::CVRegXMM10, X86::XMM10},
129+
{ codeview::RegisterId::CVRegXMM11, X86::XMM11},
130+
{ codeview::RegisterId::CVRegXMM12, X86::XMM12},
131+
{ codeview::RegisterId::CVRegXMM13, X86::XMM13},
132+
{ codeview::RegisterId::CVRegXMM14, X86::XMM14},
133+
{ codeview::RegisterId::CVRegXMM15, X86::XMM15},
134+
135+
{ codeview::RegisterId::CVRegSIL, X86::SIL},
136+
{ codeview::RegisterId::CVRegDIL, X86::DIL},
137+
{ codeview::RegisterId::CVRegBPL, X86::BPL},
138+
{ codeview::RegisterId::CVRegSPL, X86::SPL},
139+
{ codeview::RegisterId::CVRegRAX, X86::RAX},
140+
{ codeview::RegisterId::CVRegRBX, X86::RBX},
141+
{ codeview::RegisterId::CVRegRCX, X86::RCX},
142+
{ codeview::RegisterId::CVRegRDX, X86::RDX},
143+
{ codeview::RegisterId::CVRegRSI, X86::RSI},
144+
{ codeview::RegisterId::CVRegRDI, X86::RDI},
145+
{ codeview::RegisterId::CVRegRBP, X86::RBP},
146+
{ codeview::RegisterId::CVRegRSP, X86::RSP},
147+
{ codeview::RegisterId::CVRegR8, X86::R8},
148+
{ codeview::RegisterId::CVRegR9, X86::R9},
149+
{ codeview::RegisterId::CVRegR10, X86::R10},
150+
{ codeview::RegisterId::CVRegR11, X86::R11},
151+
{ codeview::RegisterId::CVRegR12, X86::R12},
152+
{ codeview::RegisterId::CVRegR13, X86::R13},
153+
{ codeview::RegisterId::CVRegR14, X86::R14},
154+
{ codeview::RegisterId::CVRegR15, X86::R15},
155+
{ codeview::RegisterId::CVRegR8B, X86::R8B},
156+
{ codeview::RegisterId::CVRegR9B, X86::R9B},
157+
{ codeview::RegisterId::CVRegR10B, X86::R10B},
158+
{ codeview::RegisterId::CVRegR11B, X86::R11B},
159+
{ codeview::RegisterId::CVRegR12B, X86::R12B},
160+
{ codeview::RegisterId::CVRegR13B, X86::R13B},
161+
{ codeview::RegisterId::CVRegR14B, X86::R14B},
162+
{ codeview::RegisterId::CVRegR15B, X86::R15B},
163+
{ codeview::RegisterId::CVRegR8W, X86::R8W},
164+
{ codeview::RegisterId::CVRegR9W, X86::R9W},
165+
{ codeview::RegisterId::CVRegR10W, X86::R10W},
166+
{ codeview::RegisterId::CVRegR11W, X86::R11W},
167+
{ codeview::RegisterId::CVRegR12W, X86::R12W},
168+
{ codeview::RegisterId::CVRegR13W, X86::R13W},
169+
{ codeview::RegisterId::CVRegR14W, X86::R14W},
170+
{ codeview::RegisterId::CVRegR15W, X86::R15W},
171+
{ codeview::RegisterId::CVRegR8D, X86::R8D},
172+
{ codeview::RegisterId::CVRegR9D, X86::R9D},
173+
{ codeview::RegisterId::CVRegR10D, X86::R10D},
174+
{ codeview::RegisterId::CVRegR11D, X86::R11D},
175+
{ codeview::RegisterId::CVRegR12D, X86::R12D},
176+
{ codeview::RegisterId::CVRegR13D, X86::R13D},
177+
{ codeview::RegisterId::CVRegR14D, X86::R14D},
178+
{ codeview::RegisterId::CVRegR15D, X86::R15D},
179+
{ codeview::RegisterId::CVRegAMD64_YMM0, X86::YMM0},
180+
{ codeview::RegisterId::CVRegAMD64_YMM1, X86::YMM1},
181+
{ codeview::RegisterId::CVRegAMD64_YMM2, X86::YMM2},
182+
{ codeview::RegisterId::CVRegAMD64_YMM3, X86::YMM3},
183+
{ codeview::RegisterId::CVRegAMD64_YMM4, X86::YMM4},
184+
{ codeview::RegisterId::CVRegAMD64_YMM5, X86::YMM5},
185+
{ codeview::RegisterId::CVRegAMD64_YMM6, X86::YMM6},
186+
{ codeview::RegisterId::CVRegAMD64_YMM7, X86::YMM7},
187+
{ codeview::RegisterId::CVRegAMD64_YMM8, X86::YMM8},
188+
{ codeview::RegisterId::CVRegAMD64_YMM9, X86::YMM9},
189+
{ codeview::RegisterId::CVRegAMD64_YMM10, X86::YMM10},
190+
{ codeview::RegisterId::CVRegAMD64_YMM11, X86::YMM11},
191+
{ codeview::RegisterId::CVRegAMD64_YMM12, X86::YMM12},
192+
{ codeview::RegisterId::CVRegAMD64_YMM13, X86::YMM13},
193+
{ codeview::RegisterId::CVRegAMD64_YMM14, X86::YMM14},
194+
{ codeview::RegisterId::CVRegAMD64_YMM15, X86::YMM15},
195195
};
196196
for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
197197
MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));

‎llvm/test/DebugInfo/COFF/fp-stack.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ entry:
1212

1313
; ASM: .cv_def_range Lfunc_begin0 Lfunc_end0, "A\021\200\000\000\000"
1414
; OBJ: DefRangeRegisterSym {
15-
; OBJ: Register: ST0 (0x80)
15+
; OBJ: Register: CVRegST0 (0x80)
1616
; OBJ: MayHaveNoName: 0
1717
; OBJ: LocalVariableAddrRange {
1818
; OBJ: OffsetStart: .text+0x0

‎llvm/test/DebugInfo/COFF/local-variable-gap.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@
7373
; OBJ-NOT: LocalSym {
7474
; OBJ: DefRangeRegisterSym {
7575
; OBJ-NEXT: Kind:
76-
; OBJ-NEXT: Register: ESI (0x17)
76+
; OBJ-NEXT: Register: CVRegESI (0x17)
7777
; OBJ-NEXT: MayHaveNoName: 0
7878
; OBJ-NEXT: LocalVariableAddrRange {
7979
; OBJ-NEXT: OffsetStart: .text+0x{{.*}}

‎llvm/test/DebugInfo/COFF/local-variables.ll

+5-5
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,7 @@
111111
; OBJ: VarName: param
112112
; OBJ: }
113113
; OBJ: DefRangeRegisterRelSym {
114-
; OBJ: BaseRegister: RSP (0x14F)
114+
; OBJ: BaseRegister: CVRegRSP (0x14F)
115115
; OBJ: HasSpilledUDTMember: No
116116
; OBJ: OffsetInParent: 0
117117
; OBJ: BasePointerOffset: 52
@@ -128,7 +128,7 @@
128128
; OBJ: VarName: a
129129
; OBJ: }
130130
; OBJ: DefRangeRegisterRelSym {
131-
; OBJ: BaseRegister: RSP (0x14F)
131+
; OBJ: BaseRegister: CVRegRSP (0x14F)
132132
; OBJ: HasSpilledUDTMember: No
133133
; OBJ: OffsetInParent: 0
134134
; OBJ: BasePointerOffset: 40
@@ -145,7 +145,7 @@
145145
; OBJ: VarName: b
146146
; OBJ: }
147147
; OBJ: DefRangeRegisterRelSym {
148-
; OBJ: BaseRegister: RSP (0x14F)
148+
; OBJ: BaseRegister: CVRegRSP (0x14F)
149149
; OBJ: HasSpilledUDTMember: No
150150
; OBJ: OffsetInParent: 0
151151
; OBJ: BasePointerOffset: 36
@@ -173,7 +173,7 @@
173173
; OBJ: VarName: v
174174
; OBJ: }
175175
; OBJ: DefRangeRegisterRelSym {
176-
; OBJ: BaseRegister: RSP (0x14F)
176+
; OBJ: BaseRegister: CVRegRSP (0x14F)
177177
; OBJ: HasSpilledUDTMember: No
178178
; OBJ: OffsetInParent: 0
179179
; OBJ: BasePointerOffset: 44
@@ -203,7 +203,7 @@
203203
; OBJ: VarName: v
204204
; OBJ: }
205205
; OBJ: DefRangeRegisterRelSym {
206-
; OBJ: BaseRegister: RSP (0x14F)
206+
; OBJ: BaseRegister: CVRegRSP (0x14F)
207207
; OBJ: HasSpilledUDTMember: No
208208
; OBJ: OffsetInParent: 0
209209
; OBJ: BasePointerOffset: 48

‎llvm/test/DebugInfo/COFF/pieces.ll

+7-7
Original file line numberDiff line numberDiff line change
@@ -116,14 +116,14 @@
116116
; OBJ: VarName: o
117117
; OBJ: }
118118
; OBJ: DefRangeSubfieldRegisterSym {
119-
; OBJ: Register: EDI (0x18)
119+
; OBJ: Register: CVRegEDI (0x18)
120120
; OBJ: MayHaveNoName: 0
121121
; OBJ: OffsetInParent: 0
122122
; OBJ: LocalVariableAddrRange {
123123
; OBJ: }
124124
; OBJ: }
125125
; OBJ: DefRangeSubfieldRegisterSym {
126-
; OBJ: Register: ESI (0x17)
126+
; OBJ: Register: CVRegESI (0x17)
127127
; OBJ: MayHaveNoName: 0
128128
; OBJ: OffsetInParent: 4
129129
; OBJ: LocalVariableAddrRange {
@@ -146,7 +146,7 @@
146146
; OBJ: VarName: o
147147
; OBJ: }
148148
; OBJ: DefRangeSubfieldRegisterSym {
149-
; OBJ: Register: ECX (0x12)
149+
; OBJ: Register: CVRegECX (0x12)
150150
; OBJ: MayHaveNoName: 0
151151
; OBJ: OffsetInParent: 4
152152
; OBJ: LocalVariableAddrRange {
@@ -169,7 +169,7 @@
169169
; OBJ: VarName: o
170170
; OBJ: }
171171
; OBJ: DefRangeSubfieldRegisterSym {
172-
; OBJ: Register: ECX (0x12)
172+
; OBJ: Register: CVRegECX (0x12)
173173
; OBJ: MayHaveNoName: 0
174174
; OBJ: OffsetInParent: 0
175175
; OBJ: LocalVariableAddrRange {
@@ -196,7 +196,7 @@
196196
; OBJ: VarName: o
197197
; OBJ: }
198198
; OBJ: DefRangeRegisterRelSym {
199-
; OBJ: BaseRegister: RCX (0x14A)
199+
; OBJ: BaseRegister: CVRegRCX (0x14A)
200200
; OBJ: HasSpilledUDTMember: No
201201
; OBJ: OffsetInParent: 0
202202
; OBJ: BasePointerOffset: 0
@@ -207,7 +207,7 @@
207207
; OBJ: VarName: p
208208
; OBJ: }
209209
; OBJ: DefRangeSubfieldRegisterSym {
210-
; OBJ: Register: EAX (0x11)
210+
; OBJ: Register: CVRegEAX (0x11)
211211
; OBJ: MayHaveNoName: 0
212212
; OBJ: OffsetInParent: 4
213213
; OBJ: LocalVariableAddrRange {
@@ -231,7 +231,7 @@
231231
; OBJ: VarName: o
232232
; OBJ: }
233233
; OBJ: DefRangeRegisterRelSym {
234-
; OBJ: BaseRegister: RSP (0x14F)
234+
; OBJ: BaseRegister: CVRegRSP (0x14F)
235235
; OBJ: HasSpilledUDTMember: Yes
236236
; OBJ: OffsetInParent: 4
237237
; OBJ: BasePointerOffset: 36

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