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sdesmalen-armsdesmalen-arm
committedApr 26, 2018
[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector) load instructions.
Patch [2/3] in series to add support for SVE's gather load instructions that use scalar+vector addressing modes: - Patch [1/3]: https://reviews.llvm.org/D45951 - Patch [2/3]: https://reviews.llvm.org/D46023 - Patch [3/3]: https://reviews.llvm.org/D45958 Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46023 llvm-svn: 330928
1 parent db31e7a commit 74f9e67

20 files changed

+852
-17
lines changed
 

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

+83-1
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,89 @@ let Predicates = [HasSVE] in {
106106
defm LD3D_IMM : sve_mem_eld_si<0b11, 0b10, ZZZ_d, "ld3d", simm4Scale3MulVl>;
107107
defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4Scale4MulVl>;
108108

109-
// continuous store with immediates
109+
// Gathers using unscaled 32-bit offsets, e.g.
110+
// ld1h z0.s, p0/z, [x0, z0.s, uxtw]
111+
defm GLD1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
112+
defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
113+
defm GLD1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
114+
defm GLDFF1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
115+
defm GLD1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
116+
defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
117+
defm GLD1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
118+
defm GLDFF1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0111, "ldff1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
119+
defm GLD1W : sve_mem_32b_gld_vs_32_unscaled<0b1010, "ld1w", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
120+
defm GLDFF1W : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
121+
122+
// Gathers using scaled 32-bit offsets, e.g.
123+
// ld1h z0.s, p0/z, [x0, z0.s, uxtw #1]
124+
defm GLD1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0100, "ld1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
125+
defm GLDFF1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0101, "ldff1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
126+
defm GLD1H_S : sve_mem_32b_gld_sv_32_scaled<0b0110, "ld1h", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
127+
defm GLDFF1H_S : sve_mem_32b_gld_sv_32_scaled<0b0111, "ldff1h", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
128+
defm GLD1W : sve_mem_32b_gld_sv_32_scaled<0b1010, "ld1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
129+
defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
130+
131+
// Gathers using unscaled 64-bit offsets, e.g.
132+
// ld1h z0.d, p0/z, [x0, z0.d]
133+
defm GLD1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0000, "ld1sb">;
134+
defm GLDFF1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0001, "ldff1sb">;
135+
defm GLD1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0010, "ld1b">;
136+
defm GLDFF1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0011, "ldff1b">;
137+
defm GLD1SH_D : sve_mem_64b_gld_vs2_64_unscaled<0b0100, "ld1sh">;
138+
defm GLDFF1SH_D : sve_mem_64b_gld_vs2_64_unscaled<0b0101, "ldff1sh">;
139+
defm GLD1H_D : sve_mem_64b_gld_vs2_64_unscaled<0b0110, "ld1h">;
140+
defm GLDFF1H_D : sve_mem_64b_gld_vs2_64_unscaled<0b0111, "ldff1h">;
141+
defm GLD1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1000, "ld1sw">;
142+
defm GLDFF1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1001, "ldff1sw">;
143+
defm GLD1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1010, "ld1w">;
144+
defm GLDFF1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w">;
145+
defm GLD1D : sve_mem_64b_gld_vs2_64_unscaled<0b1110, "ld1d">;
146+
defm GLDFF1D : sve_mem_64b_gld_vs2_64_unscaled<0b1111, "ldff1d">;
147+
148+
// Gathers using scaled 64-bit offsets, e.g.
149+
// ld1h z0.d, p0/z, [x0, z0.d, lsl #1]
150+
defm GLD1SH_D : sve_mem_64b_gld_sv2_64_scaled<0b0100, "ld1sh", ZPR64ExtLSL16>;
151+
defm GLDFF1SH_D : sve_mem_64b_gld_sv2_64_scaled<0b0101, "ldff1sh", ZPR64ExtLSL16>;
152+
defm GLD1H_D : sve_mem_64b_gld_sv2_64_scaled<0b0110, "ld1h", ZPR64ExtLSL16>;
153+
defm GLDFF1H_D : sve_mem_64b_gld_sv2_64_scaled<0b0111, "ldff1h", ZPR64ExtLSL16>;
154+
defm GLD1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1000, "ld1sw", ZPR64ExtLSL32>;
155+
defm GLDFF1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1001, "ldff1sw", ZPR64ExtLSL32>;
156+
defm GLD1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1010, "ld1w", ZPR64ExtLSL32>;
157+
defm GLDFF1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1011, "ldff1w", ZPR64ExtLSL32>;
158+
defm GLD1D : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d", ZPR64ExtLSL64>;
159+
defm GLDFF1D : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d", ZPR64ExtLSL64>;
160+
161+
// Gathers using unscaled 32-bit offsets unpacked in 64-bits elements, e.g.
162+
// ld1h z0.d, p0/z, [x0, z0.d, uxtw]
163+
defm GLD1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
164+
defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
165+
defm GLD1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
166+
defm GLDFF1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
167+
defm GLD1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
168+
defm GLDFF1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
169+
defm GLD1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
170+
defm GLDFF1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0111, "ldff1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
171+
defm GLD1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1000, "ld1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
172+
defm GLDFF1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1001, "ldff1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
173+
defm GLD1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1010, "ld1w", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
174+
defm GLDFF1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1011, "ldff1w", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
175+
defm GLD1D : sve_mem_64b_gld_vs_32_unscaled<0b1110, "ld1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
176+
defm GLDFF1D : sve_mem_64b_gld_vs_32_unscaled<0b1111, "ldff1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
177+
178+
// Gathers using scaled 32-bit offsets unpacked in 64-bits elements, e.g.
179+
// ld1h z0.d, p0/z, [x0, z0.d, uxtw #1]
180+
defm GLD1SH_D : sve_mem_64b_gld_sv_32_scaled<0b0100, "ld1sh", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
181+
defm GLDFF1SH_D : sve_mem_64b_gld_sv_32_scaled<0b0101, "ldff1sh",ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
182+
defm GLD1H_D : sve_mem_64b_gld_sv_32_scaled<0b0110, "ld1h", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
183+
defm GLDFF1H_D : sve_mem_64b_gld_sv_32_scaled<0b0111, "ldff1h", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
184+
defm GLD1SW_D : sve_mem_64b_gld_sv_32_scaled<0b1000, "ld1sw", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
185+
defm GLDFF1SW_D : sve_mem_64b_gld_sv_32_scaled<0b1001, "ldff1sw",ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
186+
defm GLD1W_D : sve_mem_64b_gld_sv_32_scaled<0b1010, "ld1w", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
187+
defm GLDFF1W_D : sve_mem_64b_gld_sv_32_scaled<0b1011, "ldff1w", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
188+
defm GLD1D : sve_mem_64b_gld_sv_32_scaled<0b1110, "ld1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
189+
defm GLDFF1D : sve_mem_64b_gld_sv_32_scaled<0b1111, "ldff1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
190+
191+
// contiguous store with immediates
110192
defm ST1B_IMM : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
111193
defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>;
112194
defm ST1B_S_IMM : sve_mem_cst_si<0b00, 0b10, "st1b", Z_s, ZPR32>;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

+129
Original file line numberDiff line numberDiff line change
@@ -760,3 +760,132 @@ multiclass sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
760760
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
761761
(!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
762762
}
763+
764+
//===----------------------------------------------------------------------===//
765+
// SVE Memory - 32-bit Gather and Unsized Contiguous Group
766+
//===----------------------------------------------------------------------===//
767+
768+
// bit xs is '1' if offsets are signed
769+
// bit scaled is '1' if the offsets are scaled
770+
class sve_mem_32b_gld_sv<bits<4> opc, bit xs, bit scaled, string asm,
771+
RegisterOperand zprext>
772+
: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
773+
asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
774+
"",
775+
[]>, Sched<[]> {
776+
bits<3> Pg;
777+
bits<5> Rn;
778+
bits<5> Zm;
779+
bits<5> Zt;
780+
let Inst{31-25} = 0b1000010;
781+
let Inst{24-23} = opc{3-2};
782+
let Inst{22} = xs;
783+
let Inst{21} = scaled;
784+
let Inst{20-16} = Zm;
785+
let Inst{15} = 0b0;
786+
let Inst{14-13} = opc{1-0};
787+
let Inst{12-10} = Pg;
788+
let Inst{9-5} = Rn;
789+
let Inst{4-0} = Zt;
790+
791+
let mayLoad = 1;
792+
let Defs = !if(!eq(opc{0}, 1), [FFR], []);
793+
let Uses = !if(!eq(opc{0}, 1), [FFR], []);
794+
}
795+
796+
multiclass sve_mem_32b_gld_sv_32_scaled<bits<4> opc, string asm,
797+
RegisterOperand sxtw_opnd,
798+
RegisterOperand uxtw_opnd> {
799+
def _UXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 0, 1, asm, uxtw_opnd>;
800+
def _SXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 1, 1, asm, sxtw_opnd>;
801+
802+
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
803+
(!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
804+
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
805+
(!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
806+
}
807+
808+
multiclass sve_mem_32b_gld_vs_32_unscaled<bits<4> opc, string asm,
809+
RegisterOperand sxtw_opnd,
810+
RegisterOperand uxtw_opnd> {
811+
def _UXTW_REAL : sve_mem_32b_gld_sv<opc, 0, 0, asm, uxtw_opnd>;
812+
def _SXTW_REAL : sve_mem_32b_gld_sv<opc, 1, 0, asm, sxtw_opnd>;
813+
814+
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
815+
(!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
816+
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
817+
(!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
818+
}
819+
820+
821+
//===----------------------------------------------------------------------===//
822+
// SVE Memory - 64-bit Gather Group
823+
//===----------------------------------------------------------------------===//
824+
825+
// bit xs is '1' if offsets are signed
826+
// bit scaled is '1' if the offsets are scaled
827+
// bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
828+
class sve_mem_64b_gld_sv<bits<4> opc, bit xs, bit scaled, bit lsl, string asm,
829+
RegisterOperand zprext>
830+
: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
831+
asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
832+
"",
833+
[]>, Sched<[]> {
834+
bits<3> Pg;
835+
bits<5> Rn;
836+
bits<5> Zm;
837+
bits<5> Zt;
838+
let Inst{31-25} = 0b1100010;
839+
let Inst{24-23} = opc{3-2};
840+
let Inst{22} = xs;
841+
let Inst{21} = scaled;
842+
let Inst{20-16} = Zm;
843+
let Inst{15} = lsl;
844+
let Inst{14-13} = opc{1-0};
845+
let Inst{12-10} = Pg;
846+
let Inst{9-5} = Rn;
847+
let Inst{4-0} = Zt;
848+
849+
let mayLoad = 1;
850+
let Defs = !if(!eq(opc{0}, 1), [FFR], []);
851+
let Uses = !if(!eq(opc{0}, 1), [FFR], []);
852+
}
853+
854+
multiclass sve_mem_64b_gld_sv_32_scaled<bits<4> opc, string asm,
855+
RegisterOperand sxtw_opnd,
856+
RegisterOperand uxtw_opnd> {
857+
def _UXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 0, 1, 0, asm, uxtw_opnd>;
858+
def _SXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 0, asm, sxtw_opnd>;
859+
860+
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
861+
(!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
862+
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
863+
(!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
864+
}
865+
866+
multiclass sve_mem_64b_gld_vs_32_unscaled<bits<4> opc, string asm,
867+
RegisterOperand sxtw_opnd,
868+
RegisterOperand uxtw_opnd> {
869+
def _UXTW_REAL : sve_mem_64b_gld_sv<opc, 0, 0, 0, asm, uxtw_opnd>;
870+
def _SXTW_REAL : sve_mem_64b_gld_sv<opc, 1, 0, 0, asm, sxtw_opnd>;
871+
872+
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
873+
(!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
874+
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
875+
(!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
876+
}
877+
878+
multiclass sve_mem_64b_gld_sv2_64_scaled<bits<4> opc, string asm,
879+
RegisterOperand zprext> {
880+
def _SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 1, asm, zprext>;
881+
882+
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
883+
(!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
884+
}
885+
886+
multiclass sve_mem_64b_gld_vs2_64_unscaled<bits<4> opc, string asm> {
887+
def _REAL : sve_mem_64b_gld_sv<opc, 1, 0, 1, asm, ZPR64ExtLSL8>;
888+
889+
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
890+
(!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
891+
}

‎llvm/test/MC/AArch64/SVE/ld1b.s

+30
Original file line numberDiff line numberDiff line change
@@ -138,3 +138,33 @@ ld1b { z23.d }, p3/z, [x13, x8]
138138
// CHECK-ENCODING: [0xb7,0x4d,0x68,0xa4]
139139
// CHECK-ERROR: instruction requires: sve
140140
// CHECK-UNKNOWN: b7 4d 68 a4 <unknown>
141+
142+
ld1b { z0.s }, p0/z, [x0, z0.s, uxtw]
143+
// CHECK-INST: ld1b { z0.s }, p0/z, [x0, z0.s, uxtw]
144+
// CHECK-ENCODING: [0x00,0x40,0x00,0x84]
145+
// CHECK-ERROR: instruction requires: sve
146+
// CHECK-UNKNOWN: 00 40 00 84 <unknown>
147+
148+
ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]
149+
// CHECK-INST: ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]
150+
// CHECK-ENCODING: [0x00,0x40,0x40,0x84]
151+
// CHECK-ERROR: instruction requires: sve
152+
// CHECK-UNKNOWN: 00 40 40 84 <unknown>
153+
154+
ld1b { z31.d }, p7/z, [sp, z31.d]
155+
// CHECK-INST: ld1b { z31.d }, p7/z, [sp, z31.d]
156+
// CHECK-ENCODING: [0xff,0xdf,0x5f,0xc4]
157+
// CHECK-ERROR: instruction requires: sve
158+
// CHECK-UNKNOWN: ff df 5f c4 <unknown>
159+
160+
ld1b { z21.d }, p5/z, [x10, z21.d, uxtw]
161+
// CHECK-INST: ld1b { z21.d }, p5/z, [x10, z21.d, uxtw]
162+
// CHECK-ENCODING: [0x55,0x55,0x15,0xc4]
163+
// CHECK-ERROR: instruction requires: sve
164+
// CHECK-UNKNOWN: 55 55 15 c4 <unknown>
165+
166+
ld1b { z21.d }, p5/z, [x10, z21.d, sxtw]
167+
// CHECK-INST: ld1b { z21.d }, p5/z, [x10, z21.d, sxtw]
168+
// CHECK-ENCODING: [0x55,0x55,0x55,0xc4]
169+
// CHECK-ERROR: instruction requires: sve
170+
// CHECK-UNKNOWN: 55 55 55 c4 <unknown>

‎llvm/test/MC/AArch64/SVE/ld1d.s

+36
Original file line numberDiff line numberDiff line change
@@ -42,3 +42,39 @@ ld1d { z23.d }, p3/z, [x13, x8, lsl #3]
4242
// CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa5]
4343
// CHECK-ERROR: instruction requires: sve
4444
// CHECK-UNKNOWN: b7 4d e8 a5 <unknown>
45+
46+
ld1d { z31.d }, p7/z, [sp, z31.d]
47+
// CHECK-INST: ld1d { z31.d }, p7/z, [sp, z31.d]
48+
// CHECK-ENCODING: [0xff,0xdf,0xdf,0xc5]
49+
// CHECK-ERROR: instruction requires: sve
50+
// CHECK-UNKNOWN: ff df df c5 <unknown>
51+
52+
ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
53+
// CHECK-INST: ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
54+
// CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc5]
55+
// CHECK-ERROR: instruction requires: sve
56+
// CHECK-UNKNOWN: b7 cd e8 c5 <unknown>
57+
58+
ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]
59+
// CHECK-INST: ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]
60+
// CHECK-ENCODING: [0x55,0x55,0x95,0xc5]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: 55 55 95 c5 <unknown>
63+
64+
ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]
65+
// CHECK-INST: ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]
66+
// CHECK-ENCODING: [0x55,0x55,0xd5,0xc5]
67+
// CHECK-ERROR: instruction requires: sve
68+
// CHECK-UNKNOWN: 55 55 d5 c5 <unknown>
69+
70+
ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
71+
// CHECK-INST: ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
72+
// CHECK-ENCODING: [0x00,0x40,0xa0,0xc5]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: 00 40 a0 c5 <unknown>
75+
76+
ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
77+
// CHECK-INST: ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
78+
// CHECK-ENCODING: [0x00,0x40,0xe0,0xc5]
79+
// CHECK-ERROR: instruction requires: sve
80+
// CHECK-UNKNOWN: 00 40 e0 c5 <unknown>

‎llvm/test/MC/AArch64/SVE/ld1h.s

+60
Original file line numberDiff line numberDiff line change
@@ -102,3 +102,63 @@ ld1h { z23.d }, p3/z, [x13, x8, lsl #1]
102102
// CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa4]
103103
// CHECK-ERROR: instruction requires: sve
104104
// CHECK-UNKNOWN: b7 4d e8 a4 <unknown>
105+
106+
ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
107+
// CHECK-INST: ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
108+
// CHECK-ENCODING: [0x00,0x40,0x80,0x84]
109+
// CHECK-ERROR: instruction requires: sve
110+
// CHECK-UNKNOWN: 00 40 80 84 <unknown>
111+
112+
ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
113+
// CHECK-INST: ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
114+
// CHECK-ENCODING: [0x00,0x40,0xc0,0x84]
115+
// CHECK-ERROR: instruction requires: sve
116+
// CHECK-UNKNOWN: 00 40 c0 84 <unknown>
117+
118+
ld1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
119+
// CHECK-INST: ld1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
120+
// CHECK-ENCODING: [0xff,0x5f,0xbf,0x84]
121+
// CHECK-ERROR: instruction requires: sve
122+
// CHECK-UNKNOWN: ff 5f bf 84 <unknown>
123+
124+
ld1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
125+
// CHECK-INST: ld1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
126+
// CHECK-ENCODING: [0xff,0x5f,0xff,0x84]
127+
// CHECK-ERROR: instruction requires: sve
128+
// CHECK-UNKNOWN: ff 5f ff 84 <unknown>
129+
130+
ld1h { z31.d }, p7/z, [sp, z31.d]
131+
// CHECK-INST: ld1h { z31.d }, p7/z, [sp, z31.d]
132+
// CHECK-ENCODING: [0xff,0xdf,0xdf,0xc4]
133+
// CHECK-ERROR: instruction requires: sve
134+
// CHECK-UNKNOWN: ff df df c4 <unknown>
135+
136+
ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
137+
// CHECK-INST: ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
138+
// CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc4]
139+
// CHECK-ERROR: instruction requires: sve
140+
// CHECK-UNKNOWN: b7 cd e8 c4 <unknown>
141+
142+
ld1h { z21.d }, p5/z, [x10, z21.d, uxtw]
143+
// CHECK-INST: ld1h { z21.d }, p5/z, [x10, z21.d, uxtw]
144+
// CHECK-ENCODING: [0x55,0x55,0x95,0xc4]
145+
// CHECK-ERROR: instruction requires: sve
146+
// CHECK-UNKNOWN: 55 55 95 c4 <unknown>
147+
148+
ld1h { z21.d }, p5/z, [x10, z21.d, sxtw]
149+
// CHECK-INST: ld1h { z21.d }, p5/z, [x10, z21.d, sxtw]
150+
// CHECK-ENCODING: [0x55,0x55,0xd5,0xc4]
151+
// CHECK-ERROR: instruction requires: sve
152+
// CHECK-UNKNOWN: 55 55 d5 c4 <unknown>
153+
154+
ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
155+
// CHECK-INST: ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
156+
// CHECK-ENCODING: [0x00,0x40,0xa0,0xc4]
157+
// CHECK-ERROR: instruction requires: sve
158+
// CHECK-UNKNOWN: 00 40 a0 c4 <unknown>
159+
160+
ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
161+
// CHECK-INST: ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
162+
// CHECK-ENCODING: [0x00,0x40,0xe0,0xc4]
163+
// CHECK-ERROR: instruction requires: sve
164+
// CHECK-UNKNOWN: 00 40 e0 c4 <unknown>

‎llvm/test/MC/AArch64/SVE/ld1sb.s

+30
Original file line numberDiff line numberDiff line change
@@ -108,3 +108,33 @@ ld1sb { z23.d }, p3/z, [x13, x8]
108108
// CHECK-ENCODING: [0xb7,0x4d,0x88,0xa5]
109109
// CHECK-ERROR: instruction requires: sve
110110
// CHECK-UNKNOWN: b7 4d 88 a5 <unknown>
111+
112+
ld1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
113+
// CHECK-INST: ld1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
114+
// CHECK-ENCODING: [0x00,0x00,0x00,0x84]
115+
// CHECK-ERROR: instruction requires: sve
116+
// CHECK-UNKNOWN: 00 00 00 84 <unknown>
117+
118+
ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
119+
// CHECK-INST: ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
120+
// CHECK-ENCODING: [0x00,0x00,0x40,0x84]
121+
// CHECK-ERROR: instruction requires: sve
122+
// CHECK-UNKNOWN: 00 00 40 84 <unknown>
123+
124+
ld1sb { z31.d }, p7/z, [sp, z31.d]
125+
// CHECK-INST: ld1sb { z31.d }, p7/z, [sp, z31.d]
126+
// CHECK-ENCODING: [0xff,0x9f,0x5f,0xc4]
127+
// CHECK-ERROR: instruction requires: sve
128+
// CHECK-UNKNOWN: ff 9f 5f c4 <unknown>
129+
130+
ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
131+
// CHECK-INST: ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
132+
// CHECK-ENCODING: [0x55,0x15,0x15,0xc4]
133+
// CHECK-ERROR: instruction requires: sve
134+
// CHECK-UNKNOWN: 55 15 15 c4 <unknown>
135+
136+
ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
137+
// CHECK-INST: ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
138+
// CHECK-ENCODING: [0x55,0x15,0x55,0xc4]
139+
// CHECK-ERROR: instruction requires: sve
140+
// CHECK-UNKNOWN: 55 15 55 c4 <unknown>

‎llvm/test/MC/AArch64/SVE/ld1sh.s

+60
Original file line numberDiff line numberDiff line change
@@ -72,3 +72,63 @@ ld1sh { z23.d }, p3/z, [x13, x8, lsl #1]
7272
// CHECK-ENCODING: [0xb7,0x4d,0x08,0xa5]
7373
// CHECK-ERROR: instruction requires: sve
7474
// CHECK-UNKNOWN: b7 4d 08 a5 <unknown>
75+
76+
ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
77+
// CHECK-INST: ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
78+
// CHECK-ENCODING: [0x00,0x00,0x80,0x84]
79+
// CHECK-ERROR: instruction requires: sve
80+
// CHECK-UNKNOWN: 00 00 80 84 <unknown>
81+
82+
ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
83+
// CHECK-INST: ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
84+
// CHECK-ENCODING: [0x00,0x00,0xc0,0x84]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: 00 00 c0 84 <unknown>
87+
88+
ld1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
89+
// CHECK-INST: ld1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
90+
// CHECK-ENCODING: [0xff,0x1f,0xbf,0x84]
91+
// CHECK-ERROR: instruction requires: sve
92+
// CHECK-UNKNOWN: ff 1f bf 84 <unknown>
93+
94+
ld1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
95+
// CHECK-INST: ld1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
96+
// CHECK-ENCODING: [0xff,0x1f,0xff,0x84]
97+
// CHECK-ERROR: instruction requires: sve
98+
// CHECK-UNKNOWN: ff 1f ff 84 <unknown>
99+
100+
ld1sh { z31.d }, p7/z, [sp, z31.d]
101+
// CHECK-INST: ld1sh { z31.d }, p7/z, [sp, z31.d]
102+
// CHECK-ENCODING: [0xff,0x9f,0xdf,0xc4]
103+
// CHECK-ERROR: instruction requires: sve
104+
// CHECK-UNKNOWN: ff 9f df c4 <unknown>
105+
106+
ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
107+
// CHECK-INST: ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
108+
// CHECK-ENCODING: [0xb7,0x8d,0xe8,0xc4]
109+
// CHECK-ERROR: instruction requires: sve
110+
// CHECK-UNKNOWN: b7 8d e8 c4 <unknown>
111+
112+
ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
113+
// CHECK-INST: ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
114+
// CHECK-ENCODING: [0x55,0x15,0x95,0xc4]
115+
// CHECK-ERROR: instruction requires: sve
116+
// CHECK-UNKNOWN: 55 15 95 c4 <unknown>
117+
118+
ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
119+
// CHECK-INST: ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
120+
// CHECK-ENCODING: [0x55,0x15,0xd5,0xc4]
121+
// CHECK-ERROR: instruction requires: sve
122+
// CHECK-UNKNOWN: 55 15 d5 c4 <unknown>
123+
124+
ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
125+
// CHECK-INST: ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
126+
// CHECK-ENCODING: [0x00,0x00,0xa0,0xc4]
127+
// CHECK-ERROR: instruction requires: sve
128+
// CHECK-UNKNOWN: 00 00 a0 c4 <unknown>
129+
130+
ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
131+
// CHECK-INST: ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
132+
// CHECK-ENCODING: [0x00,0x00,0xe0,0xc4]
133+
// CHECK-ERROR: instruction requires: sve
134+
// CHECK-UNKNOWN: 00 00 e0 c4 <unknown>

‎llvm/test/MC/AArch64/SVE/ld1sw.s

+36
Original file line numberDiff line numberDiff line change
@@ -42,3 +42,39 @@ ld1sw { z23.d }, p3/z, [x13, x8, lsl #2]
4242
// CHECK-ENCODING: [0xb7,0x4d,0x88,0xa4]
4343
// CHECK-ERROR: instruction requires: sve
4444
// CHECK-UNKNOWN: b7 4d 88 a4 <unknown>
45+
46+
ld1sw { z31.d }, p7/z, [sp, z31.d]
47+
// CHECK-INST: ld1sw { z31.d }, p7/z, [sp, z31.d]
48+
// CHECK-ENCODING: [0xff,0x9f,0x5f,0xc5]
49+
// CHECK-ERROR: instruction requires: sve
50+
// CHECK-UNKNOWN: ff 9f 5f c5 <unknown>
51+
52+
ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
53+
// CHECK-INST: ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
54+
// CHECK-ENCODING: [0xb7,0x8d,0x68,0xc5]
55+
// CHECK-ERROR: instruction requires: sve
56+
// CHECK-UNKNOWN: b7 8d 68 c5 <unknown>
57+
58+
ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
59+
// CHECK-INST: ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
60+
// CHECK-ENCODING: [0x55,0x15,0x15,0xc5]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: 55 15 15 c5 <unknown>
63+
64+
ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
65+
// CHECK-INST: ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
66+
// CHECK-ENCODING: [0x55,0x15,0x55,0xc5]
67+
// CHECK-ERROR: instruction requires: sve
68+
// CHECK-UNKNOWN: 55 15 55 c5 <unknown>
69+
70+
ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
71+
// CHECK-INST: ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
72+
// CHECK-ENCODING: [0x00,0x00,0x20,0xc5]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: 00 00 20 c5 <unknown>
75+
76+
ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
77+
// CHECK-INST: ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
78+
// CHECK-ENCODING: [0x00,0x00,0x60,0xc5]
79+
// CHECK-ERROR: instruction requires: sve
80+
// CHECK-UNKNOWN: 00 00 60 c5 <unknown>

‎llvm/test/MC/AArch64/SVE/ld1w.s

+60
Original file line numberDiff line numberDiff line change
@@ -72,3 +72,63 @@ ld1w { z23.d }, p3/z, [x13, x8, lsl #2]
7272
// CHECK-ENCODING: [0xb7,0x4d,0x68,0xa5]
7373
// CHECK-ERROR: instruction requires: sve
7474
// CHECK-UNKNOWN: b7 4d 68 a5 <unknown>
75+
76+
ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]
77+
// CHECK-INST: ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]
78+
// CHECK-ENCODING: [0x00,0x40,0x00,0x85]
79+
// CHECK-ERROR: instruction requires: sve
80+
// CHECK-UNKNOWN: 00 40 00 85 <unknown>
81+
82+
ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]
83+
// CHECK-INST: ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]
84+
// CHECK-ENCODING: [0x00,0x40,0x40,0x85]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: 00 40 40 85 <unknown>
87+
88+
ld1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
89+
// CHECK-INST: ld1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
90+
// CHECK-ENCODING: [0xff,0x5f,0x3f,0x85]
91+
// CHECK-ERROR: instruction requires: sve
92+
// CHECK-UNKNOWN: ff 5f 3f 85 <unknown>
93+
94+
ld1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
95+
// CHECK-INST: ld1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
96+
// CHECK-ENCODING: [0xff,0x5f,0x7f,0x85]
97+
// CHECK-ERROR: instruction requires: sve
98+
// CHECK-UNKNOWN: ff 5f 7f 85 <unknown>
99+
100+
ld1w { z31.d }, p7/z, [sp, z31.d]
101+
// CHECK-INST: ld1w { z31.d }, p7/z, [sp, z31.d]
102+
// CHECK-ENCODING: [0xff,0xdf,0x5f,0xc5]
103+
// CHECK-ERROR: instruction requires: sve
104+
// CHECK-UNKNOWN: ff df 5f c5 <unknown>
105+
106+
ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
107+
// CHECK-INST: ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
108+
// CHECK-ENCODING: [0xb7,0xcd,0x68,0xc5]
109+
// CHECK-ERROR: instruction requires: sve
110+
// CHECK-UNKNOWN: b7 cd 68 c5 <unknown>
111+
112+
ld1w { z21.d }, p5/z, [x10, z21.d, uxtw]
113+
// CHECK-INST: ld1w { z21.d }, p5/z, [x10, z21.d, uxtw]
114+
// CHECK-ENCODING: [0x55,0x55,0x15,0xc5]
115+
// CHECK-ERROR: instruction requires: sve
116+
// CHECK-UNKNOWN: 55 55 15 c5 <unknown>
117+
118+
ld1w { z21.d }, p5/z, [x10, z21.d, sxtw]
119+
// CHECK-INST: ld1w { z21.d }, p5/z, [x10, z21.d, sxtw]
120+
// CHECK-ENCODING: [0x55,0x55,0x55,0xc5]
121+
// CHECK-ERROR: instruction requires: sve
122+
// CHECK-UNKNOWN: 55 55 55 c5 <unknown>
123+
124+
ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
125+
// CHECK-INST: ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
126+
// CHECK-ENCODING: [0x00,0x40,0x20,0xc5]
127+
// CHECK-ERROR: instruction requires: sve
128+
// CHECK-UNKNOWN: 00 40 20 c5 <unknown>
129+
130+
ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
131+
// CHECK-INST: ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
132+
// CHECK-ENCODING: [0x00,0x40,0x60,0xc5]
133+
// CHECK-ERROR: instruction requires: sve
134+
// CHECK-UNKNOWN: 00 40 60 c5 <unknown>

‎llvm/test/MC/AArch64/SVE/ldff1b.s

+30
Original file line numberDiff line numberDiff line change
@@ -72,3 +72,33 @@ ldff1b { z0.d }, p0/z, [x0, x0]
7272
// CHECK-ENCODING: [0x00,0x60,0x60,0xa4]
7373
// CHECK-ERROR: instruction requires: sve
7474
// CHECK-UNKNOWN: 00 60 60 a4 <unknown>
75+
76+
ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw]
77+
// CHECK-INST: ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw]
78+
// CHECK-ENCODING: [0x00,0x60,0x00,0x84]
79+
// CHECK-ERROR: instruction requires: sve
80+
// CHECK-UNKNOWN: 00 60 00 84 <unknown>
81+
82+
ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw]
83+
// CHECK-INST: ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw]
84+
// CHECK-ENCODING: [0x00,0x60,0x40,0x84]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: 00 60 40 84 <unknown>
87+
88+
ldff1b { z31.d }, p7/z, [sp, z31.d]
89+
// CHECK-INST: ldff1b { z31.d }, p7/z, [sp, z31.d]
90+
// CHECK-ENCODING: [0xff,0xff,0x5f,0xc4]
91+
// CHECK-ERROR: instruction requires: sve
92+
// CHECK-UNKNOWN: ff ff 5f c4 <unknown>
93+
94+
ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw]
95+
// CHECK-INST: ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw]
96+
// CHECK-ENCODING: [0x55,0x75,0x15,0xc4]
97+
// CHECK-ERROR: instruction requires: sve
98+
// CHECK-UNKNOWN: 55 75 15 c4 <unknown>
99+
100+
ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]
101+
// CHECK-INST: ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]
102+
// CHECK-ENCODING: [0x55,0x75,0x55,0xc4]
103+
// CHECK-ERROR: instruction requires: sve
104+
// CHECK-UNKNOWN: 55 75 55 c4 <unknown>

‎llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s

+4-4
Original file line numberDiff line numberDiff line change
@@ -30,22 +30,22 @@ ldff1d z4.d, p8/z, [x0]
3030
// Invalid scalar + scalar addressing modes
3131

3232
ldff1d z0.d, p0/z, [x0, sp]
33-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
33+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
3434
// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, sp]
3535
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
3636

3737
ldff1d z0.d, p0/z, [x0, x0, lsl #1]
38-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
38+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
3939
// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, x0, lsl #1]
4040
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
4141

4242
ldff1d z0.d, p0/z, [x0, w0]
43-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
43+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
4444
// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0]
4545
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
4646

4747
ldff1d z0.d, p0/z, [x0, w0, uxtw]
48-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
48+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
4949
// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0, uxtw]
5050
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
5151

‎llvm/test/MC/AArch64/SVE/ldff1d.s

+36
Original file line numberDiff line numberDiff line change
@@ -24,3 +24,39 @@ ldff1d { z0.d }, p0/z, [x0, x0, lsl #3]
2424
// CHECK-ENCODING: [0x00,0x60,0xe0,0xa5]
2525
// CHECK-ERROR: instruction requires: sve
2626
// CHECK-UNKNOWN: 00 60 e0 a5 <unknown>
27+
28+
ldff1d { z31.d }, p7/z, [sp, z31.d]
29+
// CHECK-INST: ldff1d { z31.d }, p7/z, [sp, z31.d]
30+
// CHECK-ENCODING: [0xff,0xff,0xdf,0xc5]
31+
// CHECK-ERROR: instruction requires: sve
32+
// CHECK-UNKNOWN: ff ff df c5 <unknown>
33+
34+
ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
35+
// CHECK-INST: ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]
36+
// CHECK-ENCODING: [0xb7,0xed,0xe8,0xc5]
37+
// CHECK-ERROR: instruction requires: sve
38+
// CHECK-UNKNOWN: b7 ed e8 c5 <unknown>
39+
40+
ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]
41+
// CHECK-INST: ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]
42+
// CHECK-ENCODING: [0x55,0x75,0x95,0xc5]
43+
// CHECK-ERROR: instruction requires: sve
44+
// CHECK-UNKNOWN: 55 75 95 c5 <unknown>
45+
46+
ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]
47+
// CHECK-INST: ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]
48+
// CHECK-ENCODING: [0x55,0x75,0xd5,0xc5]
49+
// CHECK-ERROR: instruction requires: sve
50+
// CHECK-UNKNOWN: 55 75 d5 c5 <unknown>
51+
52+
ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
53+
// CHECK-INST: ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]
54+
// CHECK-ENCODING: [0x00,0x60,0xa0,0xc5]
55+
// CHECK-ERROR: instruction requires: sve
56+
// CHECK-UNKNOWN: 00 60 a0 c5 <unknown>
57+
58+
ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
59+
// CHECK-INST: ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]
60+
// CHECK-ENCODING: [0x00,0x60,0xe0,0xc5]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: 00 60 e0 c5 <unknown>

‎llvm/test/MC/AArch64/SVE/ldff1h.s

+60
Original file line numberDiff line numberDiff line change
@@ -60,3 +60,63 @@ ldff1h { z0.d }, p0/z, [x0, x0, lsl #1]
6060
// CHECK-ENCODING: [0x00,0x60,0xe0,0xa4]
6161
// CHECK-ERROR: instruction requires: sve
6262
// CHECK-UNKNOWN: 00 60 e0 a4 <unknown>
63+
64+
ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw]
65+
// CHECK-INST: ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw]
66+
// CHECK-ENCODING: [0x00,0x60,0x80,0x84]
67+
// CHECK-ERROR: instruction requires: sve
68+
// CHECK-UNKNOWN: 00 60 80 84 <unknown>
69+
70+
ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]
71+
// CHECK-INST: ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]
72+
// CHECK-ENCODING: [0x00,0x60,0xc0,0x84]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: 00 60 c0 84 <unknown>
75+
76+
ldff1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
77+
// CHECK-INST: ldff1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
78+
// CHECK-ENCODING: [0xff,0x7f,0xbf,0x84]
79+
// CHECK-ERROR: instruction requires: sve
80+
// CHECK-UNKNOWN: ff 7f bf 84 <unknown>
81+
82+
ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
83+
// CHECK-INST: ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
84+
// CHECK-ENCODING: [0xff,0x7f,0xff,0x84]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: ff 7f ff 84 <unknown>
87+
88+
ldff1h { z31.d }, p7/z, [sp, z31.d]
89+
// CHECK-INST: ldff1h { z31.d }, p7/z, [sp, z31.d]
90+
// CHECK-ENCODING: [0xff,0xff,0xdf,0xc4]
91+
// CHECK-ERROR: instruction requires: sve
92+
// CHECK-UNKNOWN: ff ff df c4 <unknown>
93+
94+
ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
95+
// CHECK-INST: ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
96+
// CHECK-ENCODING: [0xb7,0xed,0xe8,0xc4]
97+
// CHECK-ERROR: instruction requires: sve
98+
// CHECK-UNKNOWN: b7 ed e8 c4 <unknown>
99+
100+
ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]
101+
// CHECK-INST: ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]
102+
// CHECK-ENCODING: [0x55,0x75,0x95,0xc4]
103+
// CHECK-ERROR: instruction requires: sve
104+
// CHECK-UNKNOWN: 55 75 95 c4 <unknown>
105+
106+
ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]
107+
// CHECK-INST: ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]
108+
// CHECK-ENCODING: [0x55,0x75,0xd5,0xc4]
109+
// CHECK-ERROR: instruction requires: sve
110+
// CHECK-UNKNOWN: 55 75 d5 c4 <unknown>
111+
112+
ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
113+
// CHECK-INST: ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
114+
// CHECK-ENCODING: [0x00,0x60,0xa0,0xc4]
115+
// CHECK-ERROR: instruction requires: sve
116+
// CHECK-UNKNOWN: 00 60 a0 c4 <unknown>
117+
118+
ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
119+
// CHECK-INST: ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
120+
// CHECK-ENCODING: [0x00,0x60,0xe0,0xc4]
121+
// CHECK-ERROR: instruction requires: sve
122+
// CHECK-UNKNOWN: 00 60 e0 c4 <unknown>

‎llvm/test/MC/AArch64/SVE/ldff1sb.s

+30
Original file line numberDiff line numberDiff line change
@@ -60,3 +60,33 @@ ldff1sb { z0.d }, p0/z, [x0, x0]
6060
// CHECK-ENCODING: [0x00,0x60,0x80,0xa5]
6161
// CHECK-ERROR: instruction requires: sve
6262
// CHECK-UNKNOWN: 00 60 80 a5 <unknown>
63+
64+
ldff1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
65+
// CHECK-INST: ldff1sb { z0.s }, p0/z, [x0, z0.s, uxtw]
66+
// CHECK-ENCODING: [0x00,0x20,0x00,0x84]
67+
// CHECK-ERROR: instruction requires: sve
68+
// CHECK-UNKNOWN: 00 20 00 84 <unknown>
69+
70+
ldff1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
71+
// CHECK-INST: ldff1sb { z0.s }, p0/z, [x0, z0.s, sxtw]
72+
// CHECK-ENCODING: [0x00,0x20,0x40,0x84]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: 00 20 40 84 <unknown>
75+
76+
ldff1sb { z31.d }, p7/z, [sp, z31.d]
77+
// CHECK-INST: ldff1sb { z31.d }, p7/z, [sp, z31.d]
78+
// CHECK-ENCODING: [0xff,0xbf,0x5f,0xc4]
79+
// CHECK-ERROR: instruction requires: sve
80+
// CHECK-UNKNOWN: ff bf 5f c4 <unknown>
81+
82+
ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
83+
// CHECK-INST: ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
84+
// CHECK-ENCODING: [0x55,0x35,0x15,0xc4]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: 55 35 15 c4 <unknown>
87+
88+
ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
89+
// CHECK-INST: ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
90+
// CHECK-ENCODING: [0x55,0x35,0x55,0xc4]
91+
// CHECK-ERROR: instruction requires: sve
92+
// CHECK-UNKNOWN: 55 35 55 c4 <unknown>

‎llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s

+4-4
Original file line numberDiff line numberDiff line change
@@ -25,21 +25,21 @@ ldff1sh z4.d, p8/z, [x0]
2525
// Invalid scalar + scalar addressing modes
2626

2727
ldff1sh z0.s, p0/z, [x0, sp]
28-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
28+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
2929
// CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, sp]
3030
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
3131

3232
ldff1sh z0.s, p0/z, [x0, x0, lsl #2]
33-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
33+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
3434
// CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, x0, lsl #2]
3535
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
3636

3737
ldff1sh z0.s, p0/z, [x0, w0]
38-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
38+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
3939
// CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, w0]
4040
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
4141

4242
ldff1sh z0.s, p0/z, [x0, w0, uxtw]
43-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
43+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
4444
// CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, w0, uxtw]
4545
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE/ldff1sh.s

+60
Original file line numberDiff line numberDiff line change
@@ -42,3 +42,63 @@ ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1]
4242
// CHECK-ENCODING: [0x00,0x60,0x00,0xa5]
4343
// CHECK-ERROR: instruction requires: sve
4444
// CHECK-UNKNOWN: 00 60 00 a5 <unknown>
45+
46+
ldff1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
47+
// CHECK-INST: ldff1sh { z0.s }, p0/z, [x0, z0.s, uxtw]
48+
// CHECK-ENCODING: [0x00,0x20,0x80,0x84]
49+
// CHECK-ERROR: instruction requires: sve
50+
// CHECK-UNKNOWN: 00 20 80 84 <unknown>
51+
52+
ldff1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
53+
// CHECK-INST: ldff1sh { z0.s }, p0/z, [x0, z0.s, sxtw]
54+
// CHECK-ENCODING: [0x00,0x20,0xc0,0x84]
55+
// CHECK-ERROR: instruction requires: sve
56+
// CHECK-UNKNOWN: 00 20 c0 84 <unknown>
57+
58+
ldff1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
59+
// CHECK-INST: ldff1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
60+
// CHECK-ENCODING: [0xff,0x3f,0xbf,0x84]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: ff 3f bf 84 <unknown>
63+
64+
ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
65+
// CHECK-INST: ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
66+
// CHECK-ENCODING: [0xff,0x3f,0xff,0x84]
67+
// CHECK-ERROR: instruction requires: sve
68+
// CHECK-UNKNOWN: ff 3f ff 84 <unknown>
69+
70+
ldff1sh { z31.d }, p7/z, [sp, z31.d]
71+
// CHECK-INST: ldff1sh { z31.d }, p7/z, [sp, z31.d]
72+
// CHECK-ENCODING: [0xff,0xbf,0xdf,0xc4]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: ff bf df c4 <unknown>
75+
76+
ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
77+
// CHECK-INST: ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
78+
// CHECK-ENCODING: [0xb7,0xad,0xe8,0xc4]
79+
// CHECK-ERROR: instruction requires: sve
80+
// CHECK-UNKNOWN: b7 ad e8 c4 <unknown>
81+
82+
ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
83+
// CHECK-INST: ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
84+
// CHECK-ENCODING: [0x55,0x35,0x95,0xc4]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: 55 35 95 c4 <unknown>
87+
88+
ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
89+
// CHECK-INST: ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
90+
// CHECK-ENCODING: [0x55,0x35,0xd5,0xc4]
91+
// CHECK-ERROR: instruction requires: sve
92+
// CHECK-UNKNOWN: 55 35 d5 c4 <unknown>
93+
94+
ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
95+
// CHECK-INST: ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
96+
// CHECK-ENCODING: [0x00,0x20,0xa0,0xc4]
97+
// CHECK-ERROR: instruction requires: sve
98+
// CHECK-UNKNOWN: 00 20 a0 c4 <unknown>
99+
100+
ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
101+
// CHECK-INST: ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
102+
// CHECK-ENCODING: [0x00,0x20,0xe0,0xc4]
103+
// CHECK-ERROR: instruction requires: sve
104+
// CHECK-UNKNOWN: 00 20 e0 c4 <unknown>

‎llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s

+4-4
Original file line numberDiff line numberDiff line change
@@ -20,21 +20,21 @@ ldff1sw z4.d, p8/z, [x0]
2020
// Invalid scalar + scalar addressing modes
2121

2222
ldff1sw z0.d, p0/z, [x0, sp]
23-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
23+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
2424
// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, sp]
2525
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
2626

2727
ldff1sw z0.d, p0/z, [x0, x0, lsl #3]
28-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
28+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
2929
// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, x0, lsl #3]
3030
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
3131

3232
ldff1sw z0.d, p0/z, [x0, w0]
33-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
33+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
3434
// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, w0]
3535
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
3636

3737
ldff1sw z0.d, p0/z, [x0, w0, uxtw]
38-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
38+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
3939
// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, w0, uxtw]
4040
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE/ldff1sw.s

+36
Original file line numberDiff line numberDiff line change
@@ -24,3 +24,39 @@ ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2]
2424
// CHECK-ENCODING: [0x00,0x60,0x80,0xa4]
2525
// CHECK-ERROR: instruction requires: sve
2626
// CHECK-UNKNOWN: 00 60 80 a4 <unknown>
27+
28+
ldff1sw { z31.d }, p7/z, [sp, z31.d]
29+
// CHECK-INST: ldff1sw { z31.d }, p7/z, [sp, z31.d]
30+
// CHECK-ENCODING: [0xff,0xbf,0x5f,0xc5]
31+
// CHECK-ERROR: instruction requires: sve
32+
// CHECK-UNKNOWN: ff bf 5f c5 <unknown>
33+
34+
ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
35+
// CHECK-INST: ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
36+
// CHECK-ENCODING: [0xb7,0xad,0x68,0xc5]
37+
// CHECK-ERROR: instruction requires: sve
38+
// CHECK-UNKNOWN: b7 ad 68 c5 <unknown>
39+
40+
ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
41+
// CHECK-INST: ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
42+
// CHECK-ENCODING: [0x55,0x35,0x15,0xc5]
43+
// CHECK-ERROR: instruction requires: sve
44+
// CHECK-UNKNOWN: 55 35 15 c5 <unknown>
45+
46+
ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
47+
// CHECK-INST: ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
48+
// CHECK-ENCODING: [0x55,0x35,0x55,0xc5]
49+
// CHECK-ERROR: instruction requires: sve
50+
// CHECK-UNKNOWN: 55 35 55 c5 <unknown>
51+
52+
ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
53+
// CHECK-INST: ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
54+
// CHECK-ENCODING: [0x00,0x20,0x20,0xc5]
55+
// CHECK-ERROR: instruction requires: sve
56+
// CHECK-UNKNOWN: 00 20 20 c5 <unknown>
57+
58+
ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
59+
// CHECK-INST: ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
60+
// CHECK-ENCODING: [0x00,0x20,0x60,0xc5]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: 00 20 60 c5 <unknown>

‎llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s

+4-4
Original file line numberDiff line numberDiff line change
@@ -30,21 +30,21 @@ ldff1w z4.d, p8/z, [x0]
3030
// Invalid scalar + scalar addressing modes
3131

3232
ldff1w z0.s, p0/z, [x0, sp]
33-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
33+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
3434
// CHECK-NEXT: ldff1w z0.s, p0/z, [x0, sp]
3535
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
3636

3737
ldff1w z0.s, p0/z, [x0, x0, lsl #3]
38-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
38+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
3939
// CHECK-NEXT: ldff1w z0.s, p0/z, [x0, x0, lsl #3]
4040
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
4141

4242
ldff1w z0.s, p0/z, [x0, w0]
43-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
43+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
4444
// CHECK-NEXT: ldff1w z0.s, p0/z, [x0, w0]
4545
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
4646

4747
ldff1w z0.s, p0/z, [x0, w0, uxtw]
48-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
48+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
4949
// CHECK-NEXT: ldff1w z0.s, p0/z, [x0, w0, uxtw]
5050
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE/ldff1w.s

+60
Original file line numberDiff line numberDiff line change
@@ -42,3 +42,63 @@ ldff1w { z0.d }, p0/z, [x0, x0, lsl #2]
4242
// CHECK-ENCODING: [0x00,0x60,0x60,0xa5]
4343
// CHECK-ERROR: instruction requires: sve
4444
// CHECK-UNKNOWN: 00 60 60 a5 <unknown>
45+
46+
ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
47+
// CHECK-INST: ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]
48+
// CHECK-ENCODING: [0x00,0x60,0x00,0x85]
49+
// CHECK-ERROR: instruction requires: sve
50+
// CHECK-UNKNOWN: 00 60 00 85 <unknown>
51+
52+
ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]
53+
// CHECK-INST: ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]
54+
// CHECK-ENCODING: [0x00,0x60,0x40,0x85]
55+
// CHECK-ERROR: instruction requires: sve
56+
// CHECK-UNKNOWN: 00 60 40 85 <unknown>
57+
58+
ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
59+
// CHECK-INST: ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]
60+
// CHECK-ENCODING: [0xff,0x7f,0x3f,0x85]
61+
// CHECK-ERROR: instruction requires: sve
62+
// CHECK-UNKNOWN: ff 7f 3f 85 <unknown>
63+
64+
ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
65+
// CHECK-INST: ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]
66+
// CHECK-ENCODING: [0xff,0x7f,0x7f,0x85]
67+
// CHECK-ERROR: instruction requires: sve
68+
// CHECK-UNKNOWN: ff 7f 7f 85 <unknown>
69+
70+
ldff1w { z31.d }, p7/z, [sp, z31.d]
71+
// CHECK-INST: ldff1w { z31.d }, p7/z, [sp, z31.d]
72+
// CHECK-ENCODING: [0xff,0xff,0x5f,0xc5]
73+
// CHECK-ERROR: instruction requires: sve
74+
// CHECK-UNKNOWN: ff ff 5f c5 <unknown>
75+
76+
ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
77+
// CHECK-INST: ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]
78+
// CHECK-ENCODING: [0xb7,0xed,0x68,0xc5]
79+
// CHECK-ERROR: instruction requires: sve
80+
// CHECK-UNKNOWN: b7 ed 68 c5 <unknown>
81+
82+
ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]
83+
// CHECK-INST: ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]
84+
// CHECK-ENCODING: [0x55,0x75,0x15,0xc5]
85+
// CHECK-ERROR: instruction requires: sve
86+
// CHECK-UNKNOWN: 55 75 15 c5 <unknown>
87+
88+
ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]
89+
// CHECK-INST: ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]
90+
// CHECK-ENCODING: [0x55,0x75,0x55,0xc5]
91+
// CHECK-ERROR: instruction requires: sve
92+
// CHECK-UNKNOWN: 55 75 55 c5 <unknown>
93+
94+
ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
95+
// CHECK-INST: ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]
96+
// CHECK-ENCODING: [0x00,0x60,0x20,0xc5]
97+
// CHECK-ERROR: instruction requires: sve
98+
// CHECK-UNKNOWN: 00 60 20 c5 <unknown>
99+
100+
ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
101+
// CHECK-INST: ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
102+
// CHECK-ENCODING: [0x00,0x60,0x60,0xc5]
103+
// CHECK-ERROR: instruction requires: sve
104+
// CHECK-UNKNOWN: 00 60 60 c5 <unknown>

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