Skip to content

Commit f8e88af

Browse files
azhoginazhogin
committedFeb 28, 2018
[ARM] Cortex-A57 scheduler fix for ARM backend (missed 16-bit, v8.1/v8.2/v8.3, thumb and pseudo instructions)
Added missed scheduling info for ARM Cortex A57 (AArch32) to have CompleteModel with this checkCompleteness fix: https://reviews.llvm.org/D43235. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D43808 llvm-svn: 326304
·
llvmorg-21-initllvmorg-7.0.0-rc1
1 parent ddeee12 commit f8e88af

File tree

1 file changed

+33
-5
lines changed

1 file changed

+33
-5
lines changed
 

‎llvm/lib/Target/ARM/ARMScheduleA57.td

+33-5
Original file line numberDiff line numberDiff line change
@@ -125,8 +125,9 @@ def : InstRW<[WriteNoop], (instregex "(t)?BKPT$", "(t2)?CDP(2)?$",
125125
"(t2)?CPS[123]p$", "(t2)?DBG$", "(t2)?DMB$", "(t2)?DSB$", "ERET$",
126126
"(t2|t)?HINT$", "(t)?HLT$", "(t2)?HVC$", "(t2)?ISB$", "ITasm$",
127127
"(t2)?RFE(DA|DB|IA|IB)", "(t)?SETEND", "(t2)?SETPAN", "(t2)?SMC", "SPACE",
128-
"(t2)?SRS(DA|DB|IA|IB)", "SWP(B)?", "t?TRAP", "UDF$", "t2DCPS", "t2SG",
129-
"t2TT", "tCPS", "CMP_SWAP", "t?SVC", "t2IT", "CompilerBarrier")>;
128+
"(t2)?SRS(DA|DB|IA|IB)", "SWP(B)?", "t?TRAP", "(t2|t)?UDF$", "t2DCPS", "t2SG",
129+
"t2TT", "tCPS", "CMP_SWAP", "t?SVC", "t2IT", "CompilerBarrier",
130+
"t__brkdiv0")>;
130131

131132
def : InstRW<[WriteNoop], (instregex "VMRS", "VMSR", "FMSTAT")>;
132133

@@ -146,7 +147,7 @@ def : InstRW<[WriteNoop], (instregex "FLDM", "FSTM")>;
146147
// Pseudos
147148
def : InstRW<[WriteNoop], (instregex "(t2)?ABS$",
148149
"(t)?ADJCALLSTACKDOWN$", "(t)?ADJCALLSTACKUP$", "(t2|t)?Int_eh_sjlj",
149-
"tLDRpci_pic", "t2SUBS_PC_LR",
150+
"tLDRpci_pic", "(t2)?SUBS_PC_LR",
150151
"JUMPTABLE", "tInt_WIN_eh_sjlj_longjmp",
151152
"VLD(1|2)LN(d|q)(WB_fixed_|WB_register_)?Asm",
152153
"VLD(3|4)(DUP|LN)?(d|q)(WB_fixed_|WB_register_)?Asm",
@@ -279,6 +280,9 @@ def A57WriteMLA : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
279280
def A57WriteMLAL : SchedWriteRes<[A57UnitM]> { let Latency = 4; }
280281
def A57ReadMLA : SchedReadAdvance<2, [A57WriteMLA, A57WriteMLAL]>;
281282

283+
def : InstRW<[A57WriteMLA],
284+
(instregex "t2SMLAD", "t2SMLADX", "t2SMLSD", "t2SMLSDX")>;
285+
282286
def : SchedAlias<WriteMAC16, A57WriteMLA>;
283287
def : SchedAlias<WriteMAC32, A57WriteMLA>;
284288
def : SchedAlias<ReadMAC, A57ReadMLA>;
@@ -587,6 +591,8 @@ def : InstRW<[A57WriteLDM], (instregex "(t|t2|sys)?LDM(IA|DA|DB|IB)$")>;
587591
def : InstRW<[A57WriteLDM_Upd],
588592
(instregex "(t|t2|sys)?LDM(IA_UPD|DA_UPD|DB_UPD|IB_UPD|IA_RET)", "tPOP")>;
589593

594+
def : InstRW<[A57Write_5cyc_1L], (instregex "VLLDM")>;
595+
590596
// --- 3.9 Store Instructions ---
591597

592598
// Store, immed offset
@@ -705,6 +711,8 @@ def : InstRW<[A57WriteSTM], (instregex "(t2|sys|t)?STM(IA|DA|DB|IB)$")>;
705711
def : InstRW<[A57WrBackOne, A57WriteSTM_Upd],
706712
(instregex "(t2|sys|t)?STM(IA_UPD|DA_UPD|DB_UPD|IB_UPD)", "tPUSH")>;
707713

714+
def : InstRW<[A57Write_5cyc_1S], (instregex "VLSTM")>;
715+
708716
// --- 3.10 FP Data Processing Instructions ---
709717
def : SchedAlias<WriteFPALU32, A57Write_5cyc_1V>;
710718
def : SchedAlias<WriteFPALU64, A57Write_5cyc_1V>;
@@ -722,9 +730,11 @@ def : InstRW<[A57WriteVcmp],
722730
// fp convert
723731
def : InstRW<[A57Write_5cyc_1V], (instregex
724732
"VCVT(A|N|P|M)(SH|UH|SS|US|SD|UD)", "VCVT(BDH|THD|TDH)")>;
725-
733+
def : InstRW<[A57Write_5cyc_1V], (instregex "VTOSLS", "VTOUHS", "VTOULS")>;
726734
def : SchedAlias<WriteFPCVT, A57Write_5cyc_1V>;
727735

736+
def : InstRW<[A57Write_5cyc_1V], (instregex "VJCVT")>;
737+
728738
// FP round to integral
729739
def : InstRW<[A57Write_5cyc_1V], (instregex "VRINT(A|N|P|M|Z|R|X)(H|S|D)$")>;
730740

@@ -734,6 +744,8 @@ def : SchedAlias<WriteFPDIV64, A57Write_32cyc_1W>;
734744
def : SchedAlias<WriteFPSQRT32, A57Write_17cyc_1W>;
735745
def : SchedAlias<WriteFPSQRT64, A57Write_32cyc_1W>;
736746

747+
def : InstRW<[A57Write_17cyc_1W], (instregex "VSQRTH")>;
748+
737749
// FP max/min
738750
def : InstRW<[A57Write_5cyc_1V], (instregex "VMAX", "VMIN")>;
739751

@@ -767,6 +779,13 @@ def : SchedAlias<WriteFPMAC32, A57WriteVFMA>;
767779
def : SchedAlias<WriteFPMAC64, A57WriteVFMA>;
768780
def : SchedAlias<ReadFPMAC, A57ReadVFMA5>;
769781

782+
// VMLAH/VMLSH are not binded to scheduling classes by default, so here custom:
783+
def : InstRW<[A57WriteVFMA, A57ReadVFMA5, ReadFPMUL, ReadFPMUL],
784+
(instregex "VMLAH", "VMLSH", "VNMLAH", "VNMLSH")>;
785+
786+
def : InstRW<[A57WriteVMUL],
787+
(instregex "VUDOTD", "VSDOTD", "VUDOTQ", "VSDOTQ")>;
788+
770789
def : InstRW<[A57Write_3cyc_1V], (instregex "VNEG")>;
771790
def : InstRW<[A57Write_3cyc_1V], (instregex "VSEL")>;
772791

@@ -775,6 +794,8 @@ def : InstRW<[A57Write_3cyc_1V], (instregex "VSEL")>;
775794
def : InstRW<[A57Write_3cyc_1V], (instregex "FCONST(D|S|H)")>;
776795
def : InstRW<[A57Write_3cyc_1V], (instregex "VMOV(D|S|H)(cc)?$")>;
777796

797+
def : InstRW<[A57Write_3cyc_1V], (instregex "VINSH")>;
798+
778799
// 5cyc L for FP transfer, vfp to core reg,
779800
// 5cyc L for FP transfer, core reg to vfp
780801
def : SchedAlias<WriteFPMOV, A57Write_5cyc_1L>;
@@ -1062,6 +1083,11 @@ def A57ReadVQDMLAL_VecInt : SchedReadVariant<[
10621083
def : InstRW<[A57WriteVQDMLAL_VecInt, A57ReadVQDMLAL_VecInt],
10631084
(instregex "VQDMLAL", "VQDMLSL")>;
10641085

1086+
// Vector Saturating Rounding Doubling Multiply Accumulate/Subtract Long
1087+
// Scheduling info from VQDMLAL/VQDMLSL
1088+
def : InstRW<[A57WriteVQDMLAL_VecInt, A57ReadVQDMLAL_VecInt],
1089+
(instregex "VQRDMLAH", "VQRDMLSH")>;
1090+
10651091
// ASIMD multiply long
10661092
// 5cyc F0 for r0px, 4cyc F0 for r1p0 and later
10671093
def A57WriteVMULL_VecInt : SchedWriteVariant<[
@@ -1126,6 +1152,8 @@ def : InstRW<[A57Write_3cyc_1V], (instregex "VABS(fd|fq|hd|hq)")>;
11261152
def : InstRW<[A57Write_5cyc_1V], (instregex "VABD(fd|fq|hd|hq)",
11271153
"VADD(fd|fq|hd|hq)", "VPADD(f|h)", "VSUB(fd|fq|hd|hq)")>;
11281154

1155+
def : InstRW<[A57Write_5cyc_1V], (instregex "VCADD", "VCMLA")>;
1156+
11291157
// ASIMD FP compare
11301158
def : InstRW<[A57Write_5cyc_1V], (instregex "VAC(GE|GT|LE|LT)",
11311159
"VC(EQ|GE|GT|LE)(fd|fq|hd|hq)")>;
@@ -1184,7 +1212,7 @@ def : InstRW<[A57Write_3cyc_1V], (instregex "VEXT(d|q)(8|16|32|64)")>;
11841212
// ASIMD move, immed
11851213
def : InstRW<[A57Write_3cyc_1V], (instregex
11861214
"VMOV(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v1i64|v2i64|v2f32|v4f32)",
1187-
"VMOVQ0")>;
1215+
"VMOVD0", "VMOVQ0")>;
11881216

11891217
// ASIMD move, narrowing
11901218
def : InstRW<[A57Write_3cyc_1V], (instregex "VMOVN")>;

0 commit comments

Comments
 (0)
Please sign in to comment.