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author
Evandro Menezes
committedJan 30, 2018
[AArch64] Add pipeline model for Exynos M3
Add the scheduling and cost model for Exynos M3. Differential revision: https://reviews.llvm.org/D42387 llvm-svn: 323773
1 parent 4256fd0 commit 9f9daa1

10 files changed

+908
-10
lines changed
 

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -200,6 +200,7 @@ include "AArch64SchedCyclone.td"
200200
include "AArch64SchedFalkor.td"
201201
include "AArch64SchedKryo.td"
202202
include "AArch64SchedExynosM1.td"
203+
include "AArch64SchedExynosM3.td"
203204
include "AArch64SchedThunderX.td"
204205
include "AArch64SchedThunderX2T99.td"
205206

@@ -334,19 +335,19 @@ def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
334335
FeatureSlowMisaligned128Store,
335336
FeatureZCZeroing]>;
336337

337-
def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM1",
338+
def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
338339
"Samsung Exynos-M3 processors",
339340
[FeatureCRC,
340341
FeatureCrypto,
341342
FeatureCustomCheapAsMoveHandling,
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FeatureFPARMv8,
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FeatureFuseAES,
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FeatureFuseLiterals,
346+
FeatureLSLFast,
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FeatureNEON,
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FeaturePerfMon,
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FeaturePostRAScheduler,
348-
FeatureSlowMisaligned128Store,
349-
FeatureSlowPaired128,
350+
FeaturePredictableSelectIsExpensive,
350351
FeatureZCZeroing]>;
351352

352353
def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
@@ -470,7 +471,7 @@ def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
470471
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
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def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
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def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
473-
def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM3]>;
474+
def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
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def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
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def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
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def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 37 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -675,9 +675,14 @@ static bool canBeExpandedToORR(const MachineInstr &MI, unsigned BitSize) {
675675
bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
676676
if (!Subtarget.hasCustomCheapAsMoveHandling())
677677
return MI.isAsCheapAsAMove();
678-
if (Subtarget.getProcFamily() == AArch64Subtarget::ExynosM1 &&
679-
isExynosShiftLeftFast(MI))
680-
return true;
678+
679+
if (Subtarget.getProcFamily() == AArch64Subtarget::ExynosM1 ||
680+
Subtarget.getProcFamily() == AArch64Subtarget::ExynosM3) {
681+
if (isExynosResetFast(MI) || isExynosShiftLeftFast(MI))
682+
return true;
683+
else
684+
return MI.isAsCheapAsAMove();
685+
}
681686

682687
switch (MI.getOpcode()) {
683688
default:
@@ -736,6 +741,35 @@ bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
736741
llvm_unreachable("Unknown opcode to check as cheap as a move!");
737742
}
738743

744+
bool AArch64InstrInfo::isExynosResetFast(const MachineInstr &MI) const {
745+
switch (MI.getOpcode()) {
746+
default:
747+
return false;
748+
749+
case AArch64::ADR:
750+
case AArch64::ADRP:
751+
752+
case AArch64::MOVNWi:
753+
case AArch64::MOVNXi:
754+
case AArch64::MOVZWi:
755+
case AArch64::MOVZXi:
756+
return true;
757+
758+
case AArch64::MOVID:
759+
case AArch64::MOVIv2d_ns:
760+
case AArch64::MOVIv8b_ns:
761+
case AArch64::MOVIv16b_ns:
762+
return (MI.getOperand(1).getImm() == 0);
763+
764+
case AArch64::MOVIv2i32:
765+
case AArch64::MOVIv4i32:
766+
case AArch64::MOVIv4i16:
767+
case AArch64::MOVIv8i16:
768+
return (MI.getOperand(1).getImm() == 0 &&
769+
MI.getOperand(2).getImm() == 0);
770+
}
771+
}
772+
739773
bool AArch64InstrInfo::isExynosShiftLeftFast(const MachineInstr &MI) const {
740774
unsigned Imm, Shift;
741775
AArch64_AM::ShiftExtendType Ext;

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -369,6 +369,9 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
369369
insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
370370
MachineBasicBlock::iterator &It, MachineFunction &MF,
371371
const MachineOutlinerInfo &MInfo) const override;
372+
/// Returns true if the instruction sets to an immediate value that can be
373+
/// executed more efficiently.
374+
bool isExynosResetFast(const MachineInstr &MI) const;
372375
/// Returns true if the instruction has a shift left that can be executed
373376
/// more efficiently.
374377
bool isExynosShiftLeftFast(const MachineInstr &MI) const;

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