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topperctopperc
committedJan 10, 2018
[X86] Move HasNOPL to a subtarget feature bit. Plumb MCSubtargetInfo through the MCAsmBackend constructor
After D41349, we can no get a MCSubtargetInfo into the MCAsmBackend constructor. This allows us to get NOPL from a subtarget feature rather than a CPU name blacklist. Differential Revision: https://reviews.llvm.org/D41721 llvm-svn: 322227
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‎llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

+38-43
Original file line numberDiff line numberDiff line change
@@ -67,19 +67,10 @@ class X86ELFObjectWriter : public MCELFObjectTargetWriter {
6767
};
6868

6969
class X86AsmBackend : public MCAsmBackend {
70-
const StringRef CPU;
71-
bool HasNopl;
72-
const uint64_t MaxNopLength;
70+
const MCSubtargetInfo &STI;
7371
public:
74-
X86AsmBackend(const Target &T, StringRef CPU)
75-
: MCAsmBackend(), CPU(CPU),
76-
MaxNopLength((CPU == "slm" || CPU == "silvermont") ? 7 : 15) {
77-
HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
78-
CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
79-
CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
80-
CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
81-
CPU != "c3" && CPU != "c3-2" && CPU != "lakemont" && CPU != "";
82-
}
72+
X86AsmBackend(const Target &T, const MCSubtargetInfo &STI)
73+
: MCAsmBackend(), STI(STI) {}
8374

8475
unsigned getNumFixupKinds() const override {
8576
return X86::NumTargetFixupKinds;
@@ -346,14 +337,15 @@ bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
346337
};
347338

348339
// This CPU doesn't support long nops. If needed add more.
349-
// FIXME: Can we get this from the subtarget somehow?
350340
// FIXME: We could generated something better than plain 0x90.
351-
if (!HasNopl) {
341+
if (!STI.getFeatureBits()[X86::FeatureNOPL]) {
352342
for (uint64_t i = 0; i < Count; ++i)
353343
OW->write8(0x90);
354344
return true;
355345
}
356346

347+
uint64_t MaxNopLength = STI.getFeatureBits()[X86::ProcIntelSLM] ? 7 : 15;
348+
357349
// 15 is the longest single nop instruction. Emit as many 15-byte nops as
358350
// needed, then emit a nop of the remaining length.
359351
do {
@@ -377,14 +369,15 @@ namespace {
377369
class ELFX86AsmBackend : public X86AsmBackend {
378370
public:
379371
uint8_t OSABI;
380-
ELFX86AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
381-
: X86AsmBackend(T, CPU), OSABI(OSABI) {}
372+
ELFX86AsmBackend(const Target &T, uint8_t OSABI, const MCSubtargetInfo &STI)
373+
: X86AsmBackend(T, STI), OSABI(OSABI) {}
382374
};
383375

384376
class ELFX86_32AsmBackend : public ELFX86AsmBackend {
385377
public:
386-
ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
387-
: ELFX86AsmBackend(T, OSABI, CPU) {}
378+
ELFX86_32AsmBackend(const Target &T, uint8_t OSABI,
379+
const MCSubtargetInfo &STI)
380+
: ELFX86AsmBackend(T, OSABI, STI) {}
388381

389382
std::unique_ptr<MCObjectWriter>
390383
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -394,8 +387,9 @@ class ELFX86_32AsmBackend : public ELFX86AsmBackend {
394387

395388
class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
396389
public:
397-
ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
398-
: ELFX86AsmBackend(T, OSABI, CPU) {}
390+
ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI,
391+
const MCSubtargetInfo &STI)
392+
: ELFX86AsmBackend(T, OSABI, STI) {}
399393

400394
std::unique_ptr<MCObjectWriter>
401395
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -406,8 +400,9 @@ class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
406400

407401
class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {
408402
public:
409-
ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
410-
: ELFX86AsmBackend(T, OSABI, CPU) {}
403+
ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI,
404+
const MCSubtargetInfo &STI)
405+
: ELFX86AsmBackend(T, OSABI, STI) {}
411406

412407
std::unique_ptr<MCObjectWriter>
413408
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -418,8 +413,9 @@ class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {
418413

419414
class ELFX86_64AsmBackend : public ELFX86AsmBackend {
420415
public:
421-
ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
422-
: ELFX86AsmBackend(T, OSABI, CPU) {}
416+
ELFX86_64AsmBackend(const Target &T, uint8_t OSABI,
417+
const MCSubtargetInfo &STI)
418+
: ELFX86AsmBackend(T, OSABI, STI) {}
423419

424420
std::unique_ptr<MCObjectWriter>
425421
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -431,8 +427,9 @@ class WindowsX86AsmBackend : public X86AsmBackend {
431427
bool Is64Bit;
432428

433429
public:
434-
WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
435-
: X86AsmBackend(T, CPU)
430+
WindowsX86AsmBackend(const Target &T, bool is64Bit,
431+
const MCSubtargetInfo &STI)
432+
: X86AsmBackend(T, STI)
436433
, Is64Bit(is64Bit) {
437434
}
438435

@@ -790,9 +787,9 @@ class DarwinX86AsmBackend : public X86AsmBackend {
790787
}
791788

792789
public:
793-
DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
794-
bool Is64Bit)
795-
: X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
790+
DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI,
791+
const MCSubtargetInfo &STI, bool Is64Bit)
792+
: X86AsmBackend(T, STI), MRI(MRI), Is64Bit(Is64Bit) {
796793
memset(SavedRegs, 0, sizeof(SavedRegs));
797794
OffsetSize = Is64Bit ? 8 : 4;
798795
MoveInstrSize = Is64Bit ? 3 : 2;
@@ -803,8 +800,8 @@ class DarwinX86AsmBackend : public X86AsmBackend {
803800
class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
804801
public:
805802
DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
806-
StringRef CPU)
807-
: DarwinX86AsmBackend(T, MRI, CPU, false) {}
803+
const MCSubtargetInfo &STI)
804+
: DarwinX86AsmBackend(T, MRI, STI, false) {}
808805

809806
std::unique_ptr<MCObjectWriter>
810807
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -824,8 +821,8 @@ class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
824821
const MachO::CPUSubTypeX86 Subtype;
825822
public:
826823
DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
827-
StringRef CPU, MachO::CPUSubTypeX86 st)
828-
: DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {}
824+
const MCSubtargetInfo &STI, MachO::CPUSubTypeX86 st)
825+
: DarwinX86AsmBackend(T, MRI, STI, true), Subtype(st) {}
829826

830827
std::unique_ptr<MCObjectWriter>
831828
createObjectWriter(raw_pwrite_stream &OS) const override {
@@ -847,41 +844,39 @@ MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
847844
const MCRegisterInfo &MRI,
848845
const MCTargetOptions &Options) {
849846
const Triple &TheTriple = STI.getTargetTriple();
850-
StringRef CPU = STI.getCPU();
851847
if (TheTriple.isOSBinFormatMachO())
852-
return new DarwinX86_32AsmBackend(T, MRI, CPU);
848+
return new DarwinX86_32AsmBackend(T, MRI, STI);
853849

854850
if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
855-
return new WindowsX86AsmBackend(T, false, CPU);
851+
return new WindowsX86AsmBackend(T, false, STI);
856852

857853
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
858854

859855
if (TheTriple.isOSIAMCU())
860-
return new ELFX86_IAMCUAsmBackend(T, OSABI, CPU);
856+
return new ELFX86_IAMCUAsmBackend(T, OSABI, STI);
861857

862-
return new ELFX86_32AsmBackend(T, OSABI, CPU);
858+
return new ELFX86_32AsmBackend(T, OSABI, STI);
863859
}
864860

865861
MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
866862
const MCSubtargetInfo &STI,
867863
const MCRegisterInfo &MRI,
868864
const MCTargetOptions &Options) {
869865
const Triple &TheTriple = STI.getTargetTriple();
870-
StringRef CPU = STI.getCPU();
871866
if (TheTriple.isOSBinFormatMachO()) {
872867
MachO::CPUSubTypeX86 CS =
873868
StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
874869
.Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
875870
.Default(MachO::CPU_SUBTYPE_X86_64_ALL);
876-
return new DarwinX86_64AsmBackend(T, MRI, CPU, CS);
871+
return new DarwinX86_64AsmBackend(T, MRI, STI, CS);
877872
}
878873

879874
if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
880-
return new WindowsX86AsmBackend(T, true, CPU);
875+
return new WindowsX86AsmBackend(T, true, STI);
881876

882877
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
883878

884879
if (TheTriple.getEnvironment() == Triple::GNUX32)
885-
return new ELFX86_X32AsmBackend(T, OSABI, CPU);
886-
return new ELFX86_64AsmBackend(T, OSABI, CPU);
880+
return new ELFX86_X32AsmBackend(T, OSABI, STI);
881+
return new ELFX86_64AsmBackend(T, OSABI, STI);
887882
}

‎llvm/lib/Target/X86/X86.td

+35-14
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,9 @@ def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
3434
def FeatureX87 : SubtargetFeature<"x87","HasX87", "true",
3535
"Enable X87 float instructions">;
3636

37+
def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true",
38+
"Enable NOPL instruction">;
39+
3740
def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
3841
"Enable conditional move instructions">;
3942

@@ -390,16 +393,16 @@ def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16]>;
390393
def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>;
391394
def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
392395

393-
foreach P = ["i686", "pentiumpro"] in {
394-
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
395-
}
396+
def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>;
397+
def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV,
398+
FeatureNOPL]>;
396399

397400
def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX,
398-
FeatureCMOV, FeatureFXSR]>;
401+
FeatureCMOV, FeatureFXSR, FeatureNOPL]>;
399402

400403
foreach P = ["pentium3", "pentium3m"] in {
401404
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
402-
FeatureFXSR]>;
405+
FeatureFXSR, FeatureNOPL]>;
403406
}
404407

405408
// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
@@ -414,12 +417,12 @@ foreach P = ["pentium3", "pentium3m"] in {
414417

415418
def : ProcessorModel<"pentium-m", GenericPostRAModel,
416419
[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
417-
FeatureSSE2, FeatureFXSR]>;
420+
FeatureSSE2, FeatureFXSR, FeatureNOPL]>;
418421

419422
foreach P = ["pentium4", "pentium4m"] in {
420423
def : ProcessorModel<P, GenericPostRAModel,
421424
[FeatureX87, FeatureSlowUAMem16, FeatureMMX,
422-
FeatureSSE2, FeatureFXSR]>;
425+
FeatureSSE2, FeatureFXSR, FeatureNOPL]>;
423426
}
424427

425428
// Intel Quark.
@@ -428,18 +431,19 @@ def : Proc<"lakemont", []>;
428431
// Intel Core Duo.
429432
def : ProcessorModel<"yonah", SandyBridgeModel,
430433
[FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
431-
FeatureFXSR]>;
434+
FeatureFXSR, FeatureNOPL]>;
432435

433436
// NetBurst.
434437
def : ProcessorModel<"prescott", GenericPostRAModel,
435438
[FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3,
436-
FeatureFXSR]>;
439+
FeatureFXSR, FeatureNOPL]>;
437440
def : ProcessorModel<"nocona", GenericPostRAModel, [
438441
FeatureX87,
439442
FeatureSlowUAMem16,
440443
FeatureMMX,
441444
FeatureSSE3,
442445
FeatureFXSR,
446+
FeatureNOPL,
443447
FeatureCMPXCHG16B
444448
]>;
445449

@@ -450,6 +454,7 @@ def : ProcessorModel<"core2", SandyBridgeModel, [
450454
FeatureMMX,
451455
FeatureSSSE3,
452456
FeatureFXSR,
457+
FeatureNOPL,
453458
FeatureCMPXCHG16B,
454459
FeatureLAHFSAHF,
455460
FeatureMacroFusion
@@ -460,6 +465,7 @@ def : ProcessorModel<"penryn", SandyBridgeModel, [
460465
FeatureMMX,
461466
FeatureSSE41,
462467
FeatureFXSR,
468+
FeatureNOPL,
463469
FeatureCMPXCHG16B,
464470
FeatureLAHFSAHF,
465471
FeatureMacroFusion
@@ -473,6 +479,7 @@ class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
473479
FeatureMMX,
474480
FeatureSSSE3,
475481
FeatureFXSR,
482+
FeatureNOPL,
476483
FeatureCMPXCHG16B,
477484
FeatureMOVBE,
478485
FeatureLEAForSP,
@@ -492,6 +499,7 @@ class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
492499
FeatureMMX,
493500
FeatureSSE42,
494501
FeatureFXSR,
502+
FeatureNOPL,
495503
FeatureCMPXCHG16B,
496504
FeatureMOVBE,
497505
FeaturePOPCNT,
@@ -514,6 +522,7 @@ class GoldmontProc<string Name> : ProcessorModel<Name, SLMModel, [
514522
FeatureMMX,
515523
FeatureSSE42,
516524
FeatureFXSR,
525+
FeatureNOPL,
517526
FeatureCMPXCHG16B,
518527
FeatureMOVBE,
519528
FeaturePOPCNT,
@@ -543,6 +552,7 @@ class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
543552
FeatureMMX,
544553
FeatureSSE42,
545554
FeatureFXSR,
555+
FeatureNOPL,
546556
FeatureCMPXCHG16B,
547557
FeaturePOPCNT,
548558
FeatureLAHFSAHF,
@@ -558,6 +568,7 @@ class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
558568
FeatureMMX,
559569
FeatureSSE42,
560570
FeatureFXSR,
571+
FeatureNOPL,
561572
FeatureCMPXCHG16B,
562573
FeaturePOPCNT,
563574
FeatureAES,
@@ -584,6 +595,7 @@ def SNBFeatures : ProcessorFeatures<[], [
584595
FeatureMMX,
585596
FeatureAVX,
586597
FeatureFXSR,
598+
FeatureNOPL,
587599
FeatureCMPXCHG16B,
588600
FeaturePOPCNT,
589601
FeatureAES,
@@ -757,27 +769,28 @@ def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
757769
def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
758770

759771
foreach P = ["athlon", "athlon-tbird"] in {
760-
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, Feature3DNowA, FeatureSlowSHLD]>;
772+
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, Feature3DNowA,
773+
FeatureNOPL, FeatureSlowSHLD]>;
761774
}
762775

763776
foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
764777
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE1,
765-
Feature3DNowA, FeatureFXSR, FeatureSlowSHLD]>;
778+
Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureSlowSHLD]>;
766779
}
767780

768781
foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
769782
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
770-
FeatureFXSR, Feature64Bit, FeatureSlowSHLD]>;
783+
FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureSlowSHLD]>;
771784
}
772785

773786
foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
774787
def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureSSE3, Feature3DNowA,
775-
FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowSHLD]>;
788+
FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureSlowSHLD]>;
776789
}
777790

778791
foreach P = ["amdfam10", "barcelona"] in {
779792
def : Proc<P, [FeatureX87, FeatureSSE4A, Feature3DNowA, FeatureFXSR,
780-
FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
793+
FeatureNOPL, FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
781794
FeatureSlowSHLD, FeatureLAHFSAHF]>;
782795
}
783796

@@ -788,6 +801,7 @@ def : Proc<"btver1", [
788801
FeatureSSSE3,
789802
FeatureSSE4A,
790803
FeatureFXSR,
804+
FeatureNOPL,
791805
FeatureCMPXCHG16B,
792806
FeaturePRFCHW,
793807
FeatureLZCNT,
@@ -802,6 +816,7 @@ def : ProcessorModel<"btver2", BtVer2Model, [
802816
FeatureMMX,
803817
FeatureAVX,
804818
FeatureFXSR,
819+
FeatureNOPL,
805820
FeatureSSE4A,
806821
FeatureCMPXCHG16B,
807822
FeaturePRFCHW,
@@ -832,6 +847,7 @@ def : Proc<"bdver1", [
832847
FeatureMMX,
833848
FeatureAVX,
834849
FeatureFXSR,
850+
FeatureNOPL,
835851
FeatureSSE4A,
836852
FeatureLZCNT,
837853
FeaturePOPCNT,
@@ -853,6 +869,7 @@ def : Proc<"bdver2", [
853869
FeatureMMX,
854870
FeatureAVX,
855871
FeatureFXSR,
872+
FeatureNOPL,
856873
FeatureSSE4A,
857874
FeatureF16C,
858875
FeatureLZCNT,
@@ -879,6 +896,7 @@ def : Proc<"bdver3", [
879896
FeatureMMX,
880897
FeatureAVX,
881898
FeatureFXSR,
899+
FeatureNOPL,
882900
FeatureSSE4A,
883901
FeatureF16C,
884902
FeatureLZCNT,
@@ -901,6 +919,7 @@ def : Proc<"bdver4", [
901919
FeatureMMX,
902920
FeatureAVX2,
903921
FeatureFXSR,
922+
FeatureNOPL,
904923
FeatureXOP,
905924
FeatureFMA4,
906925
FeatureCMPXCHG16B,
@@ -938,6 +957,7 @@ def: ProcessorModel<"znver1", Znver1Model, [
938957
FeatureFMA,
939958
FeatureFSGSBase,
940959
FeatureFXSR,
960+
FeatureNOPL,
941961
FeatureFastLZCNT,
942962
FeatureLAHFSAHF,
943963
FeatureLZCNT,
@@ -982,6 +1002,7 @@ def : ProcessorModel<"x86-64", SandyBridgeModel, [
9821002
FeatureMMX,
9831003
FeatureSSE2,
9841004
FeatureFXSR,
1005+
FeatureNOPL,
9851006
Feature64Bit,
9861007
FeatureSlow3OpsLEA,
9871008
FeatureSlowIncDec,

‎llvm/lib/Target/X86/X86Subtarget.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -260,6 +260,7 @@ void X86Subtarget::initializeEnvironment() {
260260
X86SSELevel = NoSSE;
261261
X863DNowLevel = NoThreeDNow;
262262
HasX87 = false;
263+
HasNOPL = false;
263264
HasCMov = false;
264265
HasX86_64 = false;
265266
HasPOPCNT = false;

‎llvm/lib/Target/X86/X86Subtarget.h

+5
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,10 @@ class X86Subtarget final : public X86GenSubtargetInfo {
9292
/// True if the processor supports X87 instructions.
9393
bool HasX87;
9494

95+
/// True if this processor has NOPL instruction
96+
/// (generally pentium pro+).
97+
bool HasNOPL;
98+
9599
/// True if this processor has conditional move instructions
96100
/// (generally pentium pro+).
97101
bool HasCMov;
@@ -469,6 +473,7 @@ class X86Subtarget final : public X86GenSubtargetInfo {
469473
void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
470474

471475
bool hasX87() const { return HasX87; }
476+
bool hasNOPL() const { return HasNOPL; }
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bool hasCMov() const { return HasCMov; }
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bool hasSSE1() const { return X86SSELevel >= SSE1; }
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bool hasSSE2() const { return X86SSELevel >= SSE2; }

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