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sdesmalen-armsdesmalen-arm
committedJan 10, 2018
[AArch64][SVE] Asm: Add support for (mov|dup) of scalar
Summary: This patch adds support for 'dup' (Scalar -> SVE) and its corresponding 'mov' alias. Reviewers: fhahn, rengolin, evandro, echristo Reviewed By: fhahn Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41822 llvm-svn: 322172
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llvmorg-21-initllvmorg-7.0.0-rc1
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‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

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@@ -23,4 +23,6 @@ let Predicates = [HasSVE] in {
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defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">;
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defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">;
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defm DUP_ZR : sve_int_perm_dup_r<"dup">;
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}

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

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@@ -11,6 +11,41 @@
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SVE Permute - Cross Lane Group
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//===----------------------------------------------------------------------===//
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class sve_int_perm_dup_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
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RegisterClass srcRegType>
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: I<(outs zprty:$Zd), (ins srcRegType:$Rn),
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asm, "\t$Zd, $Rn",
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"",
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[]>, Sched<[]> {
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bits<5> Rn;
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bits<5> Zd;
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let Inst{31-24} = 0b00000101;
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let Inst{23-22} = sz8_64;
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let Inst{21-10} = 0b100000001110;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_perm_dup_r<string asm> {
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def _B : sve_int_perm_dup_r<0b00, asm, ZPR8, GPR32sp>;
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def _H : sve_int_perm_dup_r<0b01, asm, ZPR16, GPR32sp>;
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def _S : sve_int_perm_dup_r<0b10, asm, ZPR32, GPR32sp>;
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def _D : sve_int_perm_dup_r<0b11, asm, ZPR64, GPR64sp>;
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def : InstAlias<"mov $Zd, $Rn",
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(!cast<Instruction>(NAME # _B) ZPR8:$Zd, GPR32sp:$Rn), 1>;
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def : InstAlias<"mov $Zd, $Rn",
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(!cast<Instruction>(NAME # _H) ZPR16:$Zd, GPR32sp:$Rn), 1>;
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def : InstAlias<"mov $Zd, $Rn",
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(!cast<Instruction>(NAME # _S) ZPR32:$Zd, GPR32sp:$Rn), 1>;
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def : InstAlias<"mov $Zd, $Rn",
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(!cast<Instruction>(NAME # _D) ZPR64:$Zd, GPR64sp:$Rn), 1>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Integer Arithmetic - Unpredicated Group.
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//===----------------------------------------------------------------------===//

‎llvm/test/MC/AArch64/SVE/dup-diagnostics.s

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@@ -0,0 +1,19 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// input should be a 64bit scalar register
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dup z0.d, w0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: dup z0.d, w0
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// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:
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// wzr is not a valid operand to dup
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dup z0.s, wzr
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: dup z0.s, wzr
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// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:
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// xzr is not a valid operand to dup
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dup z0.d, xzr
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: dup z0.d, xzr
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// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE/dup.s

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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dup z0.b, w0
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// CHECK-INST: mov z0.b, w0
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// CHECK-ENCODING: [0x00,0x38,0x20,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 38 20 05 <unknown>
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dup z0.h, w0
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// CHECK-INST: mov z0.h, w0
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// CHECK-ENCODING: [0x00,0x38,0x60,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 38 60 05 <unknown>
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dup z0.s, w0
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// CHECK-INST: mov z0.s, w0
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// CHECK-ENCODING: [0x00,0x38,0xa0,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 38 a0 05 <unknown>
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dup z0.d, x0
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// CHECK-INST: mov z0.d, x0
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// CHECK-ENCODING: [0x00,0x38,0xe0,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 38 e0 05 <unknown>
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dup z31.h, wsp
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// CHECK-INST: mov z31.h, wsp
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// CHECK-ENCODING: [0xff,0x3b,0x60,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b 60 05 <unknown>
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dup z31.s, wsp
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// CHECK-INST: mov z31.s, wsp
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// CHECK-ENCODING: [0xff,0x3b,0xa0,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b a0 05 <unknown>
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dup z31.d, sp
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// CHECK-INST: mov z31.d, sp
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// CHECK-ENCODING: [0xff,0x3b,0xe0,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b e0 05 <unknown>
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dup z31.b, wsp
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// CHECK-INST: mov z31.b, wsp
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// CHECK-ENCODING: [0xff,0x3b,0x20,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b 20 05 <unknown>

‎llvm/test/MC/AArch64/SVE/mov-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// input should be a 64bit scalar register
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mov z0.d, w0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: mov z0.d, w0
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// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:
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// wzr is not a valid operand to mov
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mov z0.s, wzr
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: mov z0.s, wzr
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// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:
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// xzr is not a valid operand to mov
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mov z0.d, xzr
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: mov z0.d, xzr
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// CHECK-NOT: [[@LINE-3]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE/mov.s

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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mov z0.b, w0
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// CHECK-INST: mov z0.b, w0
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// CHECK-ENCODING: [0x00,0x38,0x20,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 38 20 05 <unknown>
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mov z0.h, w0
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// CHECK-INST: mov z0.h, w0
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// CHECK-ENCODING: [0x00,0x38,0x60,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 38 60 05 <unknown>
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mov z0.s, w0
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// CHECK-INST: mov z0.s, w0
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// CHECK-ENCODING: [0x00,0x38,0xa0,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 38 a0 05 <unknown>
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mov z0.d, x0
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// CHECK-INST: mov z0.d, x0
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// CHECK-ENCODING: [0x00,0x38,0xe0,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 38 e0 05 <unknown>
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mov z31.h, wsp
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// CHECK-INST: mov z31.h, wsp
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// CHECK-ENCODING: [0xff,0x3b,0x60,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b 60 05 <unknown>
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mov z31.s, wsp
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// CHECK-INST: mov z31.s, wsp
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// CHECK-ENCODING: [0xff,0x3b,0xa0,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b a0 05 <unknown>
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mov z31.d, sp
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// CHECK-INST: mov z31.d, sp
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// CHECK-ENCODING: [0xff,0x3b,0xe0,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b e0 05 <unknown>
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mov z31.b, wsp
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// CHECK-INST: mov z31.b, wsp
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// CHECK-ENCODING: [0xff,0x3b,0x20,0x05]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 3b 20 05 <unknown>

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