@@ -500,6 +500,11 @@ namespace {
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bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
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EVT LoadResultTy, EVT &ExtVT);
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+ /// Helper function to calculate whether the given Load can have its
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+ /// width reduced to ExtVT.
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+ bool isLegalNarrowLoad(LoadSDNode *LoadN, ISD::LoadExtType ExtType,
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+ EVT &ExtVT, unsigned ShAmt = 0);
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+
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/// Helper function for MergeConsecutiveStores which merges the
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/// component store chains.
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SDValue getMergeStoreChains(SmallVectorImpl<MemOpLink> &StoreNodes,
@@ -3726,6 +3731,56 @@ bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
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return true;
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}
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+ bool DAGCombiner::isLegalNarrowLoad(LoadSDNode *LoadN, ISD::LoadExtType ExtType,
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+ EVT &ExtVT, unsigned ShAmt) {
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+ // Don't transform one with multiple uses, this would require adding a new
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+ // load.
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+ if (!SDValue(LoadN, 0).hasOneUse())
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+ return false;
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+
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+ if (LegalOperations &&
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+ !TLI.isLoadExtLegal(ExtType, LoadN->getValueType(0), ExtVT))
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+ return false;
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+
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+ // Do not generate loads of non-round integer types since these can
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+ // be expensive (and would be wrong if the type is not byte sized).
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+ if (!ExtVT.isRound())
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+ return false;
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+
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+ // Don't change the width of a volatile load.
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+ if (LoadN->isVolatile())
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+ return false;
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+
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+ // Verify that we are actually reducing a load width here.
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+ if (LoadN->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits())
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+ return false;
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+
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+ // For the transform to be legal, the load must produce only two values
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+ // (the value loaded and the chain). Don't transform a pre-increment
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+ // load, for example, which produces an extra value. Otherwise the
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+ // transformation is not equivalent, and the downstream logic to replace
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+ // uses gets things wrong.
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+ if (LoadN->getNumValues() > 2)
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+ return false;
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+
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+ // If the load that we're shrinking is an extload and we're not just
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+ // discarding the extension we can't simply shrink the load. Bail.
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+ // TODO: It would be possible to merge the extensions in some cases.
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+ if (LoadN->getExtensionType() != ISD::NON_EXTLOAD &&
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+ LoadN->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
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+ return false;
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+
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+ if (!TLI.shouldReduceLoadWidth(LoadN, ExtType, ExtVT))
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+ return false;
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+
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+ // It's not possible to generate a constant of extended or untyped type.
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+ EVT PtrType = LoadN->getOperand(1).getValueType();
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+ if (PtrType == MVT::Untyped || PtrType.isExtended())
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+ return false;
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+
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+ return true;
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+ }
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+
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SDValue DAGCombiner::visitAND(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
@@ -8030,20 +8085,12 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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ExtType = ISD::ZEXTLOAD;
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ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
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}
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- if (LegalOperations && !TLI.isLoadExtLegal(ExtType, VT, ExtVT))
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- return SDValue();
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-
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- unsigned EVTBits = ExtVT.getSizeInBits();
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-
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- // Do not generate loads of non-round integer types since these can
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- // be expensive (and would be wrong if the type is not byte sized).
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- if (!ExtVT.isRound())
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- return SDValue();
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unsigned ShAmt = 0;
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if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
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if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
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ShAmt = N01->getZExtValue();
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+ unsigned EVTBits = ExtVT.getSizeInBits();
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// Is the shift amount a multiple of size of VT?
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if ((ShAmt & (EVTBits-1)) == 0) {
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N0 = N0.getOperand(0);
@@ -8080,42 +8127,12 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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}
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}
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- // If we haven't found a load, we can't narrow it. Don't transform one with
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- // multiple uses, this would require adding a new load.
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- if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
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+ // If we haven't found a load, we can't narrow it.
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+ if (!isa<LoadSDNode>(N0))
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return SDValue();
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- // Don't change the width of a volatile load.
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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- if (LN0->isVolatile())
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- return SDValue();
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-
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- // Verify that we are actually reducing a load width here.
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- if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
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- return SDValue();
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-
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- // For the transform to be legal, the load must produce only two values
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- // (the value loaded and the chain). Don't transform a pre-increment
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- // load, for example, which produces an extra value. Otherwise the
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- // transformation is not equivalent, and the downstream logic to replace
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- // uses gets things wrong.
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- if (LN0->getNumValues() > 2)
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- return SDValue();
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-
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- // If the load that we're shrinking is an extload and we're not just
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- // discarding the extension we can't simply shrink the load. Bail.
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- // TODO: It would be possible to merge the extensions in some cases.
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- if (LN0->getExtensionType() != ISD::NON_EXTLOAD &&
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- LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
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- return SDValue();
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-
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- if (!TLI.shouldReduceLoadWidth(LN0, ExtType, ExtVT))
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- return SDValue();
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-
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- EVT PtrType = N0.getOperand(1).getValueType();
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-
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- if (PtrType == MVT::Untyped || PtrType.isExtended())
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- // It's not possible to generate a constant of extended or untyped type.
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+ if (!isLegalNarrowLoad(LN0, ExtType, ExtVT, ShAmt))
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return SDValue();
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// For big endian targets, we need to adjust the offset to the pointer to
@@ -8126,6 +8143,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
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}
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+ EVT PtrType = N0.getOperand(1).getValueType();
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uint64_t PtrOff = ShAmt / 8;
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unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
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SDLoc DL(LN0);
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