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committedDec 5, 2017
[DAGCombine] isLegalNarrowLoad function (NFC)
Pull the checks upon the load out from ReduceLoadWidth into their own function. Differential Revision: https://reviews.llvm.org/D40833 llvm-svn: 319766
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‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

+60-42
Original file line numberDiff line numberDiff line change
@@ -500,6 +500,11 @@ namespace {
500500
bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
501501
EVT LoadResultTy, EVT &ExtVT);
502502

503+
/// Helper function to calculate whether the given Load can have its
504+
/// width reduced to ExtVT.
505+
bool isLegalNarrowLoad(LoadSDNode *LoadN, ISD::LoadExtType ExtType,
506+
EVT &ExtVT, unsigned ShAmt = 0);
507+
503508
/// Helper function for MergeConsecutiveStores which merges the
504509
/// component store chains.
505510
SDValue getMergeStoreChains(SmallVectorImpl<MemOpLink> &StoreNodes,
@@ -3726,6 +3731,56 @@ bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
37263731
return true;
37273732
}
37283733

3734+
bool DAGCombiner::isLegalNarrowLoad(LoadSDNode *LoadN, ISD::LoadExtType ExtType,
3735+
EVT &ExtVT, unsigned ShAmt) {
3736+
// Don't transform one with multiple uses, this would require adding a new
3737+
// load.
3738+
if (!SDValue(LoadN, 0).hasOneUse())
3739+
return false;
3740+
3741+
if (LegalOperations &&
3742+
!TLI.isLoadExtLegal(ExtType, LoadN->getValueType(0), ExtVT))
3743+
return false;
3744+
3745+
// Do not generate loads of non-round integer types since these can
3746+
// be expensive (and would be wrong if the type is not byte sized).
3747+
if (!ExtVT.isRound())
3748+
return false;
3749+
3750+
// Don't change the width of a volatile load.
3751+
if (LoadN->isVolatile())
3752+
return false;
3753+
3754+
// Verify that we are actually reducing a load width here.
3755+
if (LoadN->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits())
3756+
return false;
3757+
3758+
// For the transform to be legal, the load must produce only two values
3759+
// (the value loaded and the chain). Don't transform a pre-increment
3760+
// load, for example, which produces an extra value. Otherwise the
3761+
// transformation is not equivalent, and the downstream logic to replace
3762+
// uses gets things wrong.
3763+
if (LoadN->getNumValues() > 2)
3764+
return false;
3765+
3766+
// If the load that we're shrinking is an extload and we're not just
3767+
// discarding the extension we can't simply shrink the load. Bail.
3768+
// TODO: It would be possible to merge the extensions in some cases.
3769+
if (LoadN->getExtensionType() != ISD::NON_EXTLOAD &&
3770+
LoadN->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
3771+
return false;
3772+
3773+
if (!TLI.shouldReduceLoadWidth(LoadN, ExtType, ExtVT))
3774+
return false;
3775+
3776+
// It's not possible to generate a constant of extended or untyped type.
3777+
EVT PtrType = LoadN->getOperand(1).getValueType();
3778+
if (PtrType == MVT::Untyped || PtrType.isExtended())
3779+
return false;
3780+
3781+
return true;
3782+
}
3783+
37293784
SDValue DAGCombiner::visitAND(SDNode *N) {
37303785
SDValue N0 = N->getOperand(0);
37313786
SDValue N1 = N->getOperand(1);
@@ -8030,20 +8085,12 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
80308085
ExtType = ISD::ZEXTLOAD;
80318086
ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
80328087
}
8033-
if (LegalOperations && !TLI.isLoadExtLegal(ExtType, VT, ExtVT))
8034-
return SDValue();
8035-
8036-
unsigned EVTBits = ExtVT.getSizeInBits();
8037-
8038-
// Do not generate loads of non-round integer types since these can
8039-
// be expensive (and would be wrong if the type is not byte sized).
8040-
if (!ExtVT.isRound())
8041-
return SDValue();
80428088

80438089
unsigned ShAmt = 0;
80448090
if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
80458091
if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
80468092
ShAmt = N01->getZExtValue();
8093+
unsigned EVTBits = ExtVT.getSizeInBits();
80478094
// Is the shift amount a multiple of size of VT?
80488095
if ((ShAmt & (EVTBits-1)) == 0) {
80498096
N0 = N0.getOperand(0);
@@ -8080,42 +8127,12 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
80808127
}
80818128
}
80828129

8083-
// If we haven't found a load, we can't narrow it. Don't transform one with
8084-
// multiple uses, this would require adding a new load.
8085-
if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
8130+
// If we haven't found a load, we can't narrow it.
8131+
if (!isa<LoadSDNode>(N0))
80868132
return SDValue();
80878133

8088-
// Don't change the width of a volatile load.
80898134
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
8090-
if (LN0->isVolatile())
8091-
return SDValue();
8092-
8093-
// Verify that we are actually reducing a load width here.
8094-
if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
8095-
return SDValue();
8096-
8097-
// For the transform to be legal, the load must produce only two values
8098-
// (the value loaded and the chain). Don't transform a pre-increment
8099-
// load, for example, which produces an extra value. Otherwise the
8100-
// transformation is not equivalent, and the downstream logic to replace
8101-
// uses gets things wrong.
8102-
if (LN0->getNumValues() > 2)
8103-
return SDValue();
8104-
8105-
// If the load that we're shrinking is an extload and we're not just
8106-
// discarding the extension we can't simply shrink the load. Bail.
8107-
// TODO: It would be possible to merge the extensions in some cases.
8108-
if (LN0->getExtensionType() != ISD::NON_EXTLOAD &&
8109-
LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
8110-
return SDValue();
8111-
8112-
if (!TLI.shouldReduceLoadWidth(LN0, ExtType, ExtVT))
8113-
return SDValue();
8114-
8115-
EVT PtrType = N0.getOperand(1).getValueType();
8116-
8117-
if (PtrType == MVT::Untyped || PtrType.isExtended())
8118-
// It's not possible to generate a constant of extended or untyped type.
8135+
if (!isLegalNarrowLoad(LN0, ExtType, ExtVT, ShAmt))
81198136
return SDValue();
81208137

81218138
// For big endian targets, we need to adjust the offset to the pointer to
@@ -8126,6 +8143,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
81268143
ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
81278144
}
81288145

8146+
EVT PtrType = N0.getOperand(1).getValueType();
81298147
uint64_t PtrOff = ShAmt / 8;
81308148
unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
81318149
SDLoc DL(LN0);

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