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Commit 20350c4

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author
Evan Cheng
committedNov 27, 2006
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands. llvm-svn: 31947
·
llvmorg-21-initllvmorg-2.0.0
1 parent 5230e91 commit 20350c4

36 files changed

+400
-356
lines changed
 

‎llvm/include/llvm/CodeGen/MachineInstr.h

+8-8
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,6 @@ namespace llvm {
2727
class Value;
2828
class Function;
2929
class MachineBasicBlock;
30-
class TargetInstrInfo;
3130
class TargetInstrDescriptor;
3231
class TargetMachine;
3332
class GlobalValue;
@@ -296,7 +295,7 @@ struct MachineOperand {
296295
///
297296
class MachineInstr {
298297
short Opcode; // the opcode
299-
short NumImplicitOps; // Number of implicit operands (which
298+
unsigned short NumImplicitOps; // Number of implicit operands (which
300299
// are determined at construction time).
301300

302301
std::vector<MachineOperand> Operands; // the operands
@@ -314,19 +313,20 @@ class MachineInstr {
314313
friend struct ilist_traits<MachineInstr>;
315314

316315
public:
317-
/// MachineInstr ctor - This constructor reserves space for numOperand
318-
/// operands.
319-
MachineInstr(short Opcode, unsigned numOperands);
316+
/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
317+
/// opcode 0 and no operands.
318+
MachineInstr();
320319

321320
/// MachineInstr ctor - This constructor create a MachineInstr and add the
322-
/// implicit operands. It reserves space for numOperand operands.
323-
MachineInstr(const TargetInstrInfo &TII, short Opcode, unsigned numOperands);
321+
/// implicit operands. It reserves space for number of operands specified by
322+
/// TargetInstrDescriptor.
323+
MachineInstr(const TargetInstrDescriptor &TID);
324324

325325
/// MachineInstr ctor - Work exactly the same as the ctor above, except that
326326
/// the MachineInstr is created and added to the end of the specified basic
327327
/// block.
328328
///
329-
MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps);
329+
MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
330330

331331
~MachineInstr();
332332

‎llvm/include/llvm/CodeGen/MachineInstrBuilder.h

+21-29
Original file line numberDiff line numberDiff line change
@@ -19,10 +19,11 @@
1919

2020
#include "llvm/CodeGen/MachineBasicBlock.h"
2121
#include "llvm/CodeGen/MachineFunction.h"
22-
#include "llvm/Target/TargetMachine.h"
2322

2423
namespace llvm {
2524

25+
class TargetInstrDescriptor;
26+
2627
class MachineInstrBuilder {
2728
MachineInstr *MI;
2829
public:
@@ -83,36 +84,29 @@ class MachineInstrBuilder {
8384
};
8485

8586
/// BuildMI - Builder interface. Specify how to create the initial instruction
86-
/// itself. NumOperands is the number of operands to the machine instruction to
87-
/// allow for memory efficient representation of machine instructions.
87+
/// itself.
8888
///
89-
inline MachineInstrBuilder BuildMI(const TargetInstrInfo &TII, int Opcode,
90-
unsigned NumOperands) {
91-
return MachineInstrBuilder(new MachineInstr(TII, Opcode, NumOperands));
89+
inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID) {
90+
return MachineInstrBuilder(new MachineInstr(TID));
9291
}
9392

9493
/// BuildMI - This version of the builder sets up the first operand as a
95-
/// destination virtual register. NumOperands is the number of additional add*
96-
/// calls that are expected, not including the destination register.
94+
/// destination virtual register.
9795
///
98-
inline MachineInstrBuilder BuildMI(const TargetInstrInfo &TII, int Opcode,
99-
unsigned NumOperands, unsigned DestReg) {
100-
return MachineInstrBuilder(new MachineInstr(TII, Opcode, NumOperands+1))
101-
.addReg(DestReg, true);
96+
inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID,
97+
unsigned DestReg) {
98+
return MachineInstrBuilder(new MachineInstr(TID)).addReg(DestReg, true);
10299
}
103100

104101
/// BuildMI - This version of the builder inserts the newly-built
105102
/// instruction before the given position in the given MachineBasicBlock, and
106103
/// sets up the first operand as a destination virtual register.
107-
/// NumOperands is the number of additional add* calls that are expected,
108-
/// not including the destination register.
109104
///
110105
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
111106
MachineBasicBlock::iterator I,
112-
int Opcode, unsigned NumOperands,
107+
const TargetInstrDescriptor &TID,
113108
unsigned DestReg) {
114-
MachineInstr *MI = new MachineInstr(*BB.getParent()->getTarget().
115-
getInstrInfo(), Opcode, NumOperands+1);
109+
MachineInstr *MI = new MachineInstr(TID);
116110
BB.insert(I, MI);
117111
return MachineInstrBuilder(MI).addReg(DestReg, true);
118112
}
@@ -123,9 +117,8 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
123117
///
124118
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
125119
MachineBasicBlock::iterator I,
126-
int Opcode, unsigned NumOperands) {
127-
MachineInstr *MI = new MachineInstr(*BB.getParent()->getTarget().
128-
getInstrInfo(), Opcode, NumOperands);
120+
const TargetInstrDescriptor &TID) {
121+
MachineInstr *MI = new MachineInstr(TID);
129122
BB.insert(I, MI);
130123
return MachineInstrBuilder(MI);
131124
}
@@ -134,20 +127,19 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
134127
/// instruction at the end of the given MachineBasicBlock, and does NOT take a
135128
/// destination register.
136129
///
137-
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
138-
unsigned NumOperands) {
139-
return BuildMI(*BB, BB->end(), Opcode, NumOperands);
130+
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
131+
const TargetInstrDescriptor &TID) {
132+
return BuildMI(*BB, BB->end(), TID);
140133
}
141134

142135
/// BuildMI - This version of the builder inserts the newly-built
143136
/// instruction at the end of the given MachineBasicBlock, and sets up the first
144-
/// operand as a destination virtual register. NumOperands is the number of
145-
/// additional add* calls that are expected, not including the destination
146-
/// register.
137+
/// operand as a destination virtual register.
147138
///
148-
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
149-
unsigned NumOperands, unsigned DestReg) {
150-
return BuildMI(*BB, BB->end(), Opcode, NumOperands, DestReg);
139+
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
140+
const TargetInstrDescriptor &TID,
141+
unsigned DestReg) {
142+
return BuildMI(*BB, BB->end(), TID, DestReg);
151143
}
152144

153145
} // End llvm namespace

‎llvm/lib/CodeGen/MachineBasicBlock.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock* N) {
5252

5353

5454
MachineInstr* ilist_traits<MachineInstr>::createSentinel() {
55-
MachineInstr* dummy = new MachineInstr(0, 0);
55+
MachineInstr* dummy = new MachineInstr();
5656
LeakDetector::removeGarbageObject(dummy);
5757
return dummy;
5858
}

‎llvm/lib/CodeGen/MachineInstr.cpp

+14-20
Original file line numberDiff line numberDiff line change
@@ -32,14 +32,10 @@ namespace llvm {
3232
extern const TargetInstrDescriptor *TargetInstrDescriptors;
3333
}
3434

35-
/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
36-
/// not a resize for them. It is expected that if you use this that you call
37-
/// add* methods below to fill up the operands, instead of the Set methods.
38-
/// Eventually, the "resizing" ctors will be phased out.
39-
///
40-
MachineInstr::MachineInstr(short opcode, unsigned numOperands)
41-
: Opcode(opcode), NumImplicitOps(0), parent(0) {
42-
Operands.reserve(numOperands);
35+
/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
36+
/// opcode 0 and no operands.
37+
MachineInstr::MachineInstr()
38+
: Opcode(0), NumImplicitOps(0), parent(0) {
4339
// Make sure that we get added to a machine basicblock
4440
LeakDetector::addGarbageObject(this);
4541
}
@@ -72,18 +68,18 @@ void MachineInstr::addImplicitDefUseOperands(const TargetInstrDescriptor &TID) {
7268
}
7369

7470
/// MachineInstr ctor - This constructor create a MachineInstr and add the
75-
/// implicit operands. It reserves space for numOperand operands.
76-
MachineInstr::MachineInstr(const TargetInstrInfo &TII, short opcode,
77-
unsigned numOperands)
78-
: Opcode(opcode), NumImplicitOps(0), parent(0) {
79-
const TargetInstrDescriptor &TID = TII.get(opcode);
71+
/// implicit operands. It reserves space for number of operands specified by
72+
/// TargetInstrDescriptor or the numOperands if it is not zero. (for
73+
/// instructions with variable number of operands).
74+
MachineInstr::MachineInstr(const TargetInstrDescriptor &TID)
75+
: Opcode(TID.Opcode), NumImplicitOps(0), parent(0) {
8076
if (TID.ImplicitDefs)
8177
for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs)
8278
NumImplicitOps++;
8379
if (TID.ImplicitUses)
8480
for (const unsigned *ImpUses = TID.ImplicitUses; *ImpUses; ++ImpUses)
8581
NumImplicitOps++;
86-
Operands.reserve(NumImplicitOps + numOperands);
82+
Operands.reserve(NumImplicitOps + TID.numOperands);
8783
addImplicitDefUseOperands(TID);
8884
// Make sure that we get added to a machine basicblock
8985
LeakDetector::addGarbageObject(this);
@@ -92,19 +88,17 @@ MachineInstr::MachineInstr(const TargetInstrInfo &TII, short opcode,
9288
/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
9389
/// MachineInstr is created and added to the end of the specified basic block.
9490
///
95-
MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
96-
unsigned numOperands)
97-
: Opcode(opcode), NumImplicitOps(0), parent(0) {
91+
MachineInstr::MachineInstr(MachineBasicBlock *MBB,
92+
const TargetInstrDescriptor &TID)
93+
: Opcode(TID.Opcode), NumImplicitOps(0), parent(0) {
9894
assert(MBB && "Cannot use inserting ctor with null basic block!");
99-
const TargetInstrDescriptor &TID = MBB->getParent()->getTarget().
100-
getInstrInfo()->get(opcode);
10195
if (TID.ImplicitDefs)
10296
for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs)
10397
NumImplicitOps++;
10498
if (TID.ImplicitUses)
10599
for (const unsigned *ImpUses = TID.ImplicitUses; *ImpUses; ++ImpUses)
106100
NumImplicitOps++;
107-
Operands.reserve(NumImplicitOps + numOperands);
101+
Operands.reserve(NumImplicitOps + TID.numOperands);
108102
addImplicitDefUseOperands(TID);
109103
// Make sure that we get added to a machine basicblock
110104
LeakDetector::addGarbageObject(this);

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -395,7 +395,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
395395
#endif
396396

397397
// Create the new machine instruction.
398-
MachineInstr *MI = new MachineInstr(*TII, Opc, NumMIOperands);
398+
MachineInstr *MI = new MachineInstr(II);
399399

400400
// Add result register values for things that are defined by this
401401
// instruction.
@@ -518,7 +518,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
518518

519519
// Create the inline asm machine instruction.
520520
MachineInstr *MI =
521-
new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
521+
new MachineInstr(BB, TII->get(TargetInstrInfo::INLINEASM));
522522

523523
// Add the asm string as an external symbol operand.
524524
const char *AsmStr =

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -294,8 +294,9 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
294294
}
295295
unsigned PHIReg = ValueMap[PN];
296296
assert(PHIReg && "PHI node does not have an assigned virtual register!");
297+
const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
297298
for (unsigned i = 0; i != NumElements; ++i)
298-
BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
299+
BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
299300
}
300301
}
301302
}

‎llvm/lib/Target/ARM/ARMInstrInfo.cpp

+3-2
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,8 @@
1919
using namespace llvm;
2020

2121
ARMInstrInfo::ARMInstrInfo()
22-
: TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
22+
: TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])),
23+
RI(*this) {
2324
}
2425

2526
const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
@@ -54,5 +55,5 @@ void ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
5455
const std::vector<MachineOperand> &Cond)const{
5556
// Can only insert uncond branches so far.
5657
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
57-
BuildMI(&MBB, ARM::b, 1).addMBB(TBB);
58+
BuildMI(&MBB, get(ARM::b)).addMBB(TBB);
5859
}

‎llvm/lib/Target/ARM/ARMMul.cpp

+4-2
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,8 @@
1616
#include "ARM.h"
1717
#include "llvm/CodeGen/MachineInstrBuilder.h"
1818
#include "llvm/CodeGen/MachineFunctionPass.h"
19+
#include "llvm/Target/TargetMachine.h"
20+
#include "llvm/Target/TargetInstrInfo.h"
1921
#include "llvm/Support/Compiler.h"
2022

2123
using namespace llvm;
@@ -60,8 +62,8 @@ bool FixMul::runOnMachineFunction(MachineFunction &MF) {
6062
RsOp.setReg(Rm);
6163
} else {
6264
unsigned scratch = Op == ARM::MUL ? ARM::R12 : ARM::R0;
63-
BuildMI(MBB, I, ARM::MOV, 3, scratch).addReg(Rm).addImm(0)
64-
.addImm(ARMShift::LSL);
65+
BuildMI(MBB, I, MF.getTarget().getInstrInfo()->get(ARM::MOV),
66+
scratch).addReg(Rm).addImm(0).addImm(ARMShift::LSL);
6567
RmOp.setReg(scratch);
6668
}
6769
}

‎llvm/lib/Target/ARM/ARMRegisterInfo.cpp

+18-16
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#include "llvm/Target/TargetFrameInfo.h"
2323
#include "llvm/Target/TargetMachine.h"
2424
#include "llvm/Target/TargetOptions.h"
25+
#include "llvm/Target/TargetInstrInfo.h"
2526
#include "llvm/ADT/STLExtras.h"
2627
#include <iostream>
2728
using namespace llvm;
@@ -35,24 +36,25 @@ static bool hasFP(const MachineFunction &MF) {
3536
return NoFramePointerElim || MFI->hasVarSizedObjects();
3637
}
3738

38-
ARMRegisterInfo::ARMRegisterInfo()
39-
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
39+
ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii)
40+
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
41+
TII(tii) {
4042
}
4143

4244
void ARMRegisterInfo::
4345
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
4446
unsigned SrcReg, int FI,
4547
const TargetRegisterClass *RC) const {
4648
assert (RC == ARM::IntRegsRegisterClass);
47-
BuildMI(MBB, I, ARM::STR, 3).addReg(SrcReg).addFrameIndex(FI).addImm(0);
49+
BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI).addImm(0);
4850
}
4951

5052
void ARMRegisterInfo::
5153
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
5254
unsigned DestReg, int FI,
5355
const TargetRegisterClass *RC) const {
5456
assert (RC == ARM::IntRegsRegisterClass);
55-
BuildMI(MBB, I, ARM::LDR, 2, DestReg).addFrameIndex(FI).addImm(0);
57+
BuildMI(MBB, I, TII.get(ARM::LDR), DestReg).addFrameIndex(FI).addImm(0);
5658
}
5759

5860
void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
@@ -64,12 +66,12 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
6466
RC == ARM::DFPRegsRegisterClass);
6567

6668
if (RC == ARM::IntRegsRegisterClass)
67-
BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
69+
BuildMI(MBB, I, TII.get(ARM::MOV), DestReg).addReg(SrcReg).addImm(0)
6870
.addImm(ARMShift::LSL);
6971
else if (RC == ARM::FPRegsRegisterClass)
70-
BuildMI(MBB, I, ARM::FCPYS, 1, DestReg).addReg(SrcReg);
72+
BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
7173
else
72-
BuildMI(MBB, I, ARM::FCPYD, 1, DestReg).addReg(SrcReg);
74+
BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
7375
}
7476

7577
MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
@@ -109,12 +111,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
109111

110112
if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
111113
// sub sp, sp, amount
112-
BuildMI(MBB, I, ARM::SUB, 2, ARM::R13).addReg(ARM::R13).addImm(Amount)
114+
BuildMI(MBB, I, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(Amount)
113115
.addImm(0).addImm(ARMShift::LSL);
114116
} else {
115117
// add sp, sp, amount
116118
assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
117-
BuildMI(MBB, I, ARM::ADD, 2, ARM::R13).addReg(ARM::R13).addImm(Amount)
119+
BuildMI(MBB, I, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(Amount)
118120
.addImm(0).addImm(ARMShift::LSL);
119121
}
120122
}
@@ -155,7 +157,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
155157
// Insert a set of r12 with the full address
156158
// r12 = r13 + offset
157159
MachineBasicBlock *MBB2 = MI.getParent();
158-
BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(BaseRegister)
160+
BuildMI(*MBB2, II, TII.get(ARM::ADD), ARM::R12).addReg(BaseRegister)
159161
.addImm(Offset).addImm(0).addImm(ARMShift::LSL);
160162

161163
// Replace the FrameIndex with r12
@@ -191,13 +193,13 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
191193
MFI->setStackSize(NumBytes);
192194

193195
//sub sp, sp, #NumBytes
194-
BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
196+
BuildMI(MBB, MBBI, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
195197
.addImm(0).addImm(ARMShift::LSL);
196198

197199
if (HasFP) {
198-
BuildMI(MBB, MBBI, ARM::STR, 3)
200+
BuildMI(MBB, MBBI, TII.get(ARM::STR))
199201
.addReg(ARM::R11).addReg(ARM::R13).addImm(0);
200-
BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R11).addReg(ARM::R13).addImm(0).
202+
BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R11).addReg(ARM::R13).addImm(0).
201203
addImm(ARMShift::LSL);
202204
}
203205
}
@@ -212,13 +214,13 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
212214
int NumBytes = (int) MFI->getStackSize();
213215

214216
if (hasFP(MF)) {
215-
BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R13).addReg(ARM::R11).addImm(0).
217+
BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R13).addReg(ARM::R11).addImm(0).
216218
addImm(ARMShift::LSL);
217-
BuildMI(MBB, MBBI, ARM::LDR, 2, ARM::R11).addReg(ARM::R13).addImm(0);
219+
BuildMI(MBB, MBBI, TII.get(ARM::LDR), ARM::R11).addReg(ARM::R13).addImm(0);
218220
}
219221

220222
//add sp, sp, #NumBytes
221-
BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
223+
BuildMI(MBB, MBBI, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
222224
.addImm(0).addImm(ARMShift::LSL);
223225
}
224226

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