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#include " llvm/Target/TargetFrameInfo.h"
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#include " llvm/Target/TargetMachine.h"
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#include " llvm/Target/TargetOptions.h"
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+ #include " llvm/Target/TargetInstrInfo.h"
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#include " llvm/ADT/STLExtras.h"
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#include < iostream>
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using namespace llvm ;
@@ -35,24 +36,25 @@ static bool hasFP(const MachineFunction &MF) {
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return NoFramePointerElim || MFI->hasVarSizedObjects ();
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}
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- ARMRegisterInfo::ARMRegisterInfo ()
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- : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
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+ ARMRegisterInfo::ARMRegisterInfo (const TargetInstrInfo &tii)
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+ : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
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+ TII(tii) {
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}
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void ARMRegisterInfo::
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storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, int FI,
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const TargetRegisterClass *RC) const {
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assert (RC == ARM::IntRegsRegisterClass);
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- BuildMI (MBB, I, ARM::STR, 3 ).addReg (SrcReg).addFrameIndex (FI).addImm (0 );
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+ BuildMI (MBB, I, TII. get ( ARM::STR) ).addReg (SrcReg).addFrameIndex (FI).addImm (0 );
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}
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void ARMRegisterInfo::
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loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const {
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assert (RC == ARM::IntRegsRegisterClass);
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- BuildMI (MBB, I, ARM::LDR, 2 , DestReg).addFrameIndex (FI).addImm (0 );
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+ BuildMI (MBB, I, TII. get ( ARM::LDR) , DestReg).addFrameIndex (FI).addImm (0 );
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}
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void ARMRegisterInfo::copyRegToReg (MachineBasicBlock &MBB,
@@ -64,12 +66,12 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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RC == ARM::DFPRegsRegisterClass);
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if (RC == ARM::IntRegsRegisterClass)
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- BuildMI (MBB, I, ARM::MOV, 3 , DestReg).addReg (SrcReg).addImm (0 )
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+ BuildMI (MBB, I, TII. get ( ARM::MOV) , DestReg).addReg (SrcReg).addImm (0 )
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.addImm (ARMShift::LSL);
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else if (RC == ARM::FPRegsRegisterClass)
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- BuildMI (MBB, I, ARM::FCPYS, 1 , DestReg).addReg (SrcReg);
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+ BuildMI (MBB, I, TII. get ( ARM::FCPYS) , DestReg).addReg (SrcReg);
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else
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- BuildMI (MBB, I, ARM::FCPYD, 1 , DestReg).addReg (SrcReg);
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+ BuildMI (MBB, I, TII. get ( ARM::FCPYD) , DestReg).addReg (SrcReg);
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}
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MachineInstr *ARMRegisterInfo::foldMemoryOperand (MachineInstr* MI,
@@ -109,12 +111,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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if (Old->getOpcode () == ARM::ADJCALLSTACKDOWN) {
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// sub sp, sp, amount
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- BuildMI (MBB, I, ARM::SUB, 2 , ARM::R13).addReg (ARM::R13).addImm (Amount)
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+ BuildMI (MBB, I, TII. get ( ARM::SUB) , ARM::R13).addReg (ARM::R13).addImm (Amount)
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.addImm (0 ).addImm (ARMShift::LSL);
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} else {
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// add sp, sp, amount
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assert (Old->getOpcode () == ARM::ADJCALLSTACKUP);
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- BuildMI (MBB, I, ARM::ADD, 2 , ARM::R13).addReg (ARM::R13).addImm (Amount)
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+ BuildMI (MBB, I, TII. get ( ARM::ADD) , ARM::R13).addReg (ARM::R13).addImm (Amount)
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.addImm (0 ).addImm (ARMShift::LSL);
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}
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}
@@ -155,7 +157,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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// Insert a set of r12 with the full address
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// r12 = r13 + offset
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MachineBasicBlock *MBB2 = MI.getParent ();
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- BuildMI (*MBB2, II, ARM::ADD, 4 , ARM::R12).addReg (BaseRegister)
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+ BuildMI (*MBB2, II, TII. get ( ARM::ADD) , ARM::R12).addReg (BaseRegister)
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.addImm (Offset).addImm (0 ).addImm (ARMShift::LSL);
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// Replace the FrameIndex with r12
@@ -191,13 +193,13 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MFI->setStackSize (NumBytes);
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// sub sp, sp, #NumBytes
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- BuildMI (MBB, MBBI, ARM::SUB, 4 , ARM::R13).addReg (ARM::R13).addImm (NumBytes)
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+ BuildMI (MBB, MBBI, TII. get ( ARM::SUB) , ARM::R13).addReg (ARM::R13).addImm (NumBytes)
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.addImm (0 ).addImm (ARMShift::LSL);
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if (HasFP) {
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- BuildMI (MBB, MBBI, ARM::STR, 3 )
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+ BuildMI (MBB, MBBI, TII. get ( ARM::STR) )
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.addReg (ARM::R11).addReg (ARM::R13).addImm (0 );
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- BuildMI (MBB, MBBI, ARM::MOV, 3 , ARM::R11).addReg (ARM::R13).addImm (0 ).
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+ BuildMI (MBB, MBBI, TII. get ( ARM::MOV) , ARM::R11).addReg (ARM::R13).addImm (0 ).
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addImm (ARMShift::LSL);
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}
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}
@@ -212,13 +214,13 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
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int NumBytes = (int ) MFI->getStackSize ();
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if (hasFP (MF)) {
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- BuildMI (MBB, MBBI, ARM::MOV, 3 , ARM::R13).addReg (ARM::R11).addImm (0 ).
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+ BuildMI (MBB, MBBI, TII. get ( ARM::MOV) , ARM::R13).addReg (ARM::R11).addImm (0 ).
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addImm (ARMShift::LSL);
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- BuildMI (MBB, MBBI, ARM::LDR, 2 , ARM::R11).addReg (ARM::R13).addImm (0 );
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+ BuildMI (MBB, MBBI, TII. get ( ARM::LDR) , ARM::R11).addReg (ARM::R13).addImm (0 );
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}
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// add sp, sp, #NumBytes
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- BuildMI (MBB, MBBI, ARM::ADD, 4 , ARM::R13).addReg (ARM::R13).addImm (NumBytes)
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+ BuildMI (MBB, MBBI, TII. get ( ARM::ADD) , ARM::R13).addReg (ARM::R13).addImm (NumBytes)
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.addImm (0 ).addImm (ARMShift::LSL);
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}
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