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dsandersllvmdsandersllvm
committedNov 15, 2017
Add backend name to Target to enable runtime info to be fed back into TableGen
Summary: Make it possible to feed runtime information back to tablegen to enable profile-guided tablegen-eration, detection of untested tablegen definitions, etc. Being a cross-compiler by nature, LLVM will potentially collect data for multiple architectures (e.g. when running 'ninja check'). We therefore need a way for TableGen to figure out what data applies to the backend it is generating at the time. This patch achieves that by including the name of the 'def X : Target ...' for the backend in the TargetRegistry. Reviewers: qcolombet Reviewed By: qcolombet Subscribers: jholewinski, arsenm, jyknight, aditya_nandakumar, sdardis, nemanjai, ab, nhaehnle, t.p.northover, javed.absar, qcolombet, llvm-commits, fedor.sergeev Differential Revision: https://reviews.llvm.org/D39742 llvm-svn: 318352
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16 files changed

+58
-40
lines changed

16 files changed

+58
-40
lines changed
 

Diff for: ‎llvm/include/llvm/Support/TargetRegistry.h

+16-2
Original file line numberDiff line numberDiff line change
@@ -187,6 +187,10 @@ class Target {
187187
/// ShortDesc - A short description of the target.
188188
const char *ShortDesc;
189189

190+
/// BackendName - The name of the backend implementation. This must match the
191+
/// name of the 'def X : Target ...' in TableGen.
192+
const char *BackendName;
193+
190194
/// HasJIT - Whether this target supports the JIT.
191195
bool HasJIT;
192196

@@ -279,6 +283,9 @@ class Target {
279283
/// getShortDescription - Get a short description of the target.
280284
const char *getShortDescription() const { return ShortDesc; }
281285

286+
/// getBackendName - Get the backend name.
287+
const char *getBackendName() const { return BackendName; }
288+
282289
/// @}
283290
/// @name Feature Predicates
284291
/// @{
@@ -645,10 +652,15 @@ struct TargetRegistry {
645652
/// @param Name - The target name. This should be a static string.
646653
/// @param ShortDesc - A short target description. This should be a static
647654
/// string.
655+
/// @param BackendName - The name of the backend. This should be a static
656+
/// string that is the same for all targets that share a backend
657+
/// implementation and must match the name used in the 'def X : Target ...' in
658+
/// TableGen.
648659
/// @param ArchMatchFn - The arch match checking function for this target.
649660
/// @param HasJIT - Whether the target supports JIT code
650661
/// generation.
651662
static void RegisterTarget(Target &T, const char *Name, const char *ShortDesc,
663+
const char *BackendName,
652664
Target::ArchMatchFnTy ArchMatchFn,
653665
bool HasJIT = false);
654666

@@ -883,8 +895,10 @@ struct TargetRegistry {
883895
template <Triple::ArchType TargetArchType = Triple::UnknownArch,
884896
bool HasJIT = false>
885897
struct RegisterTarget {
886-
RegisterTarget(Target &T, const char *Name, const char *Desc) {
887-
TargetRegistry::RegisterTarget(T, Name, Desc, &getArchMatch, HasJIT);
898+
RegisterTarget(Target &T, const char *Name, const char *Desc,
899+
const char *BackendName) {
900+
TargetRegistry::RegisterTarget(T, Name, Desc, BackendName, &getArchMatch,
901+
HasJIT);
888902
}
889903

890904
static bool getArchMatch(Triple::ArchType Arch) {

Diff for: ‎llvm/lib/Support/TargetRegistry.cpp

+3-2
Original file line numberDiff line numberDiff line change
@@ -86,9 +86,9 @@ const Target *TargetRegistry::lookupTarget(const std::string &TT,
8686
return &*I;
8787
}
8888

89-
void TargetRegistry::RegisterTarget(Target &T,
90-
const char *Name,
89+
void TargetRegistry::RegisterTarget(Target &T, const char *Name,
9190
const char *ShortDesc,
91+
const char *BackendName,
9292
Target::ArchMatchFnTy ArchMatchFn,
9393
bool HasJIT) {
9494
assert(Name && ShortDesc && ArchMatchFn &&
@@ -105,6 +105,7 @@ void TargetRegistry::RegisterTarget(Target &T,
105105

106106
T.Name = Name;
107107
T.ShortDesc = ShortDesc;
108+
T.BackendName = BackendName;
108109
T.ArchMatchFn = ArchMatchFn;
109110
T.HasJIT = HasJIT;
110111
}

Diff for: ‎llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -29,11 +29,11 @@ extern "C" void LLVMInitializeAArch64TargetInfo() {
2929
// Now register the "arm64" name for use with "-march". We don't want it to
3030
// take possession of the Triple::aarch64 tag though.
3131
TargetRegistry::RegisterTarget(getTheARM64Target(), "arm64",
32-
"ARM64 (little endian)",
32+
"ARM64 (little endian)", "AArch64",
3333
[](Triple::ArchType) { return false; }, true);
3434

3535
RegisterTarget<Triple::aarch64, /*HasJIT=*/true> Z(
36-
getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)");
36+
getTheAArch64leTarget(), "aarch64", "AArch64 (little endian)", "AArch64");
3737
RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true> W(
38-
getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)");
38+
getTheAArch64beTarget(), "aarch64_be", "AArch64 (big endian)", "AArch64");
3939
}

Diff for: ‎llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ Target &llvm::getTheGCNTarget() {
3131
/// \brief Extern function to initialize the targets for the AMDGPU backend
3232
extern "C" void LLVMInitializeAMDGPUTargetInfo() {
3333
RegisterTarget<Triple::r600, false> R600(getTheAMDGPUTarget(), "r600",
34-
"AMD GPUs HD2XXX-HD6XXX");
34+
"AMD GPUs HD2XXX-HD6XXX", "AMDGPU");
3535
RegisterTarget<Triple::amdgcn, false> GCN(getTheGCNTarget(), "amdgcn",
36-
"AMD GCN GPUs");
36+
"AMD GCN GPUs", "AMDGPU");
3737
}

Diff for: ‎llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -30,12 +30,12 @@ Target &llvm::getTheThumbBETarget() {
3030

3131
extern "C" void LLVMInitializeARMTargetInfo() {
3232
RegisterTarget<Triple::arm, /*HasJIT=*/true> X(getTheARMLETarget(), "arm",
33-
"ARM");
33+
"ARM", "ARM");
3434
RegisterTarget<Triple::armeb, /*HasJIT=*/true> Y(getTheARMBETarget(), "armeb",
35-
"ARM (big endian)");
35+
"ARM (big endian)", "ARM");
3636

3737
RegisterTarget<Triple::thumb, /*HasJIT=*/true> A(getTheThumbLETarget(),
38-
"thumb", "Thumb");
38+
"thumb", "Thumb", "ARM");
3939
RegisterTarget<Triple::thumbeb, /*HasJIT=*/true> B(
40-
getTheThumbBETarget(), "thumbeb", "Thumb (big endian)");
40+
getTheThumbBETarget(), "thumbeb", "Thumb (big endian)", "ARM");
4141
}

Diff for: ‎llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.cpp

+5-4
Original file line numberDiff line numberDiff line change
@@ -28,9 +28,10 @@ Target &getTheBPFTarget() {
2828

2929
extern "C" void LLVMInitializeBPFTargetInfo() {
3030
TargetRegistry::RegisterTarget(getTheBPFTarget(), "bpf", "BPF (host endian)",
31-
[](Triple::ArchType) { return false; }, true);
32-
RegisterTarget<Triple::bpfel, /*HasJIT=*/true> X(getTheBPFleTarget(), "bpfel",
33-
"BPF (little endian)");
31+
"BPF", [](Triple::ArchType) { return false; },
32+
true);
33+
RegisterTarget<Triple::bpfel, /*HasJIT=*/true> X(
34+
getTheBPFleTarget(), "bpfel", "BPF (little endian)", "BPF");
3435
RegisterTarget<Triple::bpfeb, /*HasJIT=*/true> Y(getTheBPFbeTarget(), "bpfeb",
35-
"BPF (big endian)");
36+
"BPF (big endian)", "BPF");
3637
}

Diff for: ‎llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,6 @@ Target &llvm::getTheHexagonTarget() {
1818
}
1919

2020
extern "C" void LLVMInitializeHexagonTargetInfo() {
21-
RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(getTheHexagonTarget(),
22-
"hexagon", "Hexagon");
21+
RegisterTarget<Triple::hexagon, /*HasJIT=*/false> X(
22+
getTheHexagonTarget(), "hexagon", "Hexagon", "Hexagon");
2323
}

Diff for: ‎llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -21,5 +21,6 @@ Target &getTheLanaiTarget() {
2121
} // namespace llvm
2222

2323
extern "C" void LLVMInitializeLanaiTargetInfo() {
24-
RegisterTarget<Triple::lanai> X(getTheLanaiTarget(), "lanai", "Lanai");
24+
RegisterTarget<Triple::lanai> X(getTheLanaiTarget(), "lanai", "Lanai",
25+
"Lanai");
2526
}

Diff for: ‎llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -19,5 +19,5 @@ Target &llvm::getTheMSP430Target() {
1919

2020
extern "C" void LLVMInitializeMSP430TargetInfo() {
2121
RegisterTarget<Triple::msp430> X(getTheMSP430Target(), "msp430",
22-
"MSP430 [experimental]");
22+
"MSP430 [experimental]", "MSP430");
2323
}

Diff for: ‎llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -32,17 +32,17 @@ Target &llvm::getTheMips64elTarget() {
3232
extern "C" void LLVMInitializeMipsTargetInfo() {
3333
RegisterTarget<Triple::mips,
3434
/*HasJIT=*/true>
35-
X(getTheMipsTarget(), "mips", "Mips");
35+
X(getTheMipsTarget(), "mips", "Mips", "Mips");
3636

3737
RegisterTarget<Triple::mipsel,
3838
/*HasJIT=*/true>
39-
Y(getTheMipselTarget(), "mipsel", "Mipsel");
39+
Y(getTheMipselTarget(), "mipsel", "Mipsel", "Mips");
4040

4141
RegisterTarget<Triple::mips64,
4242
/*HasJIT=*/true>
43-
A(getTheMips64Target(), "mips64", "Mips64 [experimental]");
43+
A(getTheMips64Target(), "mips64", "Mips64 [experimental]", "Mips");
4444

4545
RegisterTarget<Triple::mips64el,
4646
/*HasJIT=*/true>
47-
B(getTheMips64elTarget(), "mips64el", "Mips64el [experimental]");
47+
B(getTheMips64elTarget(), "mips64el", "Mips64el [experimental]", "Mips");
4848
}

Diff for: ‎llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ Target &llvm::getTheNVPTXTarget64() {
2323

2424
extern "C" void LLVMInitializeNVPTXTargetInfo() {
2525
RegisterTarget<Triple::nvptx> X(getTheNVPTXTarget32(), "nvptx",
26-
"NVIDIA PTX 32-bit");
26+
"NVIDIA PTX 32-bit", "NVPTX");
2727
RegisterTarget<Triple::nvptx64> Y(getTheNVPTXTarget64(), "nvptx64",
28-
"NVIDIA PTX 64-bit");
28+
"NVIDIA PTX 64-bit", "NVPTX");
2929
}

Diff for: ‎llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -27,11 +27,11 @@ Target &llvm::getThePPC64LETarget() {
2727

2828
extern "C" void LLVMInitializePowerPCTargetInfo() {
2929
RegisterTarget<Triple::ppc, /*HasJIT=*/true> X(getThePPC32Target(), "ppc32",
30-
"PowerPC 32");
30+
"PowerPC 32", "PPC");
3131

3232
RegisterTarget<Triple::ppc64, /*HasJIT=*/true> Y(getThePPC64Target(), "ppc64",
33-
"PowerPC 64");
33+
"PowerPC 64", "PPC");
3434

3535
RegisterTarget<Triple::ppc64le, /*HasJIT=*/true> Z(
36-
getThePPC64LETarget(), "ppc64le", "PowerPC 64 LE");
36+
getThePPC64LETarget(), "ppc64le", "PowerPC 64 LE", "PPC");
3737
}

Diff for: ‎llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp

+5-5
Original file line numberDiff line numberDiff line change
@@ -27,9 +27,9 @@ Target &llvm::getTheSparcelTarget() {
2727

2828
extern "C" void LLVMInitializeSparcTargetInfo() {
2929
RegisterTarget<Triple::sparc, /*HasJIT=*/true> X(getTheSparcTarget(), "sparc",
30-
"Sparc");
31-
RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(getTheSparcV9Target(),
32-
"sparcv9", "Sparc V9");
33-
RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(getTheSparcelTarget(),
34-
"sparcel", "Sparc LE");
30+
"Sparc", "Sparc");
31+
RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(
32+
getTheSparcV9Target(), "sparcv9", "Sparc V9", "Sparc");
33+
RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(
34+
getTheSparcelTarget(), "sparcel", "Sparc LE", "Sparc");
3535
}

Diff for: ‎llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,6 @@ Target &llvm::getTheSystemZTarget() {
1818
}
1919

2020
extern "C" void LLVMInitializeSystemZTargetInfo() {
21-
RegisterTarget<Triple::systemz, /*HasJIT=*/true> X(getTheSystemZTarget(),
22-
"systemz", "SystemZ");
21+
RegisterTarget<Triple::systemz, /*HasJIT=*/true> X(
22+
getTheSystemZTarget(), "systemz", "SystemZ", "SystemZ");
2323
}

Diff for: ‎llvm/lib/Target/X86/TargetInfo/X86TargetInfo.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -22,8 +22,8 @@ Target &llvm::getTheX86_64Target() {
2222

2323
extern "C" void LLVMInitializeX86TargetInfo() {
2424
RegisterTarget<Triple::x86, /*HasJIT=*/true> X(
25-
getTheX86_32Target(), "x86", "32-bit X86: Pentium-Pro and above");
25+
getTheX86_32Target(), "x86", "32-bit X86: Pentium-Pro and above", "X86");
2626

2727
RegisterTarget<Triple::x86_64, /*HasJIT=*/true> Y(
28-
getTheX86_64Target(), "x86-64", "64-bit X86: EM64T and AMD64");
28+
getTheX86_64Target(), "x86-64", "64-bit X86: EM64T and AMD64", "X86");
2929
}

Diff for: ‎llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -18,5 +18,6 @@ Target &llvm::getTheXCoreTarget() {
1818
}
1919

2020
extern "C" void LLVMInitializeXCoreTargetInfo() {
21-
RegisterTarget<Triple::xcore> X(getTheXCoreTarget(), "xcore", "XCore");
21+
RegisterTarget<Triple::xcore> X(getTheXCoreTarget(), "xcore", "XCore",
22+
"XCore");
2223
}

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