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committedOct 11, 2017
[x86] avoid infinite loop from SoftenFloatOperand (PR34866)
Legalization of fp128 assumes things that we should have asserts for, so that's another potential improvement. Differential Revision: https://reviews.llvm.org/D38771 llvm-svn: 315485
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‎llvm/lib/Target/X86/X86ISelLowering.cpp

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Original file line numberDiff line numberDiff line change
@@ -35214,6 +35214,11 @@ static SDValue combineVectorSizedSetCCEquality(SDNode *SetCC, SelectionDAG &DAG,
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if (!OpVT.isScalarInteger() || OpSize < 128 || isNullConstant(Y))
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return SDValue();
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// Bail out if we know that this is not really just an oversized integer.
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if (peekThroughBitcasts(X).getValueType() == MVT::f128 ||
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peekThroughBitcasts(Y).getValueType() == MVT::f128)
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return SDValue();
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// TODO: Use PXOR + PTEST for SSE4.1 or later?
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// TODO: Add support for AVX-512.
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EVT VT = SetCC->getValueType(0);

‎llvm/test/CodeGen/X86/fp128-cast.ll

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@@ -1,5 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=-mmx | FileCheck %s --check-prefix=X64_NO_MMX
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; RUN: llc < %s -O2 -mtriple=i686-linux-gnu -mattr=+mmx | FileCheck %s --check-prefix=X32
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; Check soft floating point conversion function calls.
@@ -359,6 +361,69 @@ cleanup: ; preds = %entry, %if.then
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; X64: retq
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}
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define i1 @PR34866(i128 %x) {
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; X64-LABEL: PR34866:
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; X64: # BB#0:
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; X64-NEXT: movaps {{.*}}(%rip), %xmm0
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; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
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; X64-NEXT: xorq -{{[0-9]+}}(%rsp), %rsi
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; X64-NEXT: xorq -{{[0-9]+}}(%rsp), %rdi
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; X64-NEXT: orq %rsi, %rdi
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; X64-NEXT: sete %al
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; X64-NEXT: retq
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;
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; X64_NO_MMX-LABEL: PR34866:
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; X64_NO_MMX: # BB#0:
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; X64_NO_MMX-NEXT: orq %rsi, %rdi
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; X64_NO_MMX-NEXT: sete %al
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; X64_NO_MMX-NEXT: retq
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;
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; X32-LABEL: PR34866:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: orl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: orl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: orl %ecx, %eax
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; X32-NEXT: sete %al
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; X32-NEXT: retl
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%bc_mmx = bitcast fp128 0xL00000000000000000000000000000000 to i128
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%cmp = icmp eq i128 %bc_mmx, %x
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ret i1 %cmp
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}
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define i1 @PR34866_commute(i128 %x) {
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; X64-LABEL: PR34866_commute:
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; X64: # BB#0:
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; X64-NEXT: movaps {{.*}}(%rip), %xmm0
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; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
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; X64-NEXT: xorq -{{[0-9]+}}(%rsp), %rsi
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; X64-NEXT: xorq -{{[0-9]+}}(%rsp), %rdi
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; X64-NEXT: orq %rsi, %rdi
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; X64-NEXT: sete %al
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; X64-NEXT: retq
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;
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; X64_NO_MMX-LABEL: PR34866_commute:
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; X64_NO_MMX: # BB#0:
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; X64_NO_MMX-NEXT: orq %rsi, %rdi
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; X64_NO_MMX-NEXT: sete %al
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; X64_NO_MMX-NEXT: retq
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;
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; X32-LABEL: PR34866_commute:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: orl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: orl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: orl %ecx, %eax
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; X32-NEXT: sete %al
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; X32-NEXT: retl
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%bc_mmx = bitcast fp128 0xL00000000000000000000000000000000 to i128
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%cmp = icmp eq i128 %x, %bc_mmx
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ret i1 %cmp
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}
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declare double @copysign(double, double) #1
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attributes #2 = { nounwind readnone }

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